Test device for testing integrated circuits

• US 5,034,685 A
• Filed: 11/14/1989
• Issued: 07/23/1991
• Est. Priority Date: 05/16/1988
• Status: Expired due to Fees

• Current Assignee: ELM TECHNOLOGY CORPORATION
• Original Assignee: Glenn J. Leedy
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Wieder, Kenneth A.
• Assistant Examiner(s): Nguyen, Vinh P.
• Application Number:
  US07/436,396
• Time in Patent Office: 616 Days
• Field of Search: 324/158 F, 324/158 P, 324/158 R, 324/158 D, 324/73.1, 437/8, 439/482
• US Class Current: 324/754.09
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/31912 Tester/user interface
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias

Abstract

Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By CAD, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of CAD. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level. The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure. The tester surface traces are then connected, by means of multiplexers, to a conventional tester signal processor.

Claims

1. A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising:

a support for a wafer to be tested, said wafer having integrated circuit logic units including electrical devices and circuitry and contact points formed thereon;

a flexible tester surface having a thickness of no greater than 15 microns and having a number of probe points corresponding to said contact points of said wafer;

means for electrically interconnecting said probe points of said flexible tester surface and said contact points of said wafer; and

means for supplying programmable input/output diagnostic signals to said flexible tester surface for testing the electrical devices and circuitry of said wafer.

2. The test device of claim 1, wherein said flexible tester surface comprises at least one thin sheet of flexible material.

3. The test device of claim 2, wherein said thin sheet comprises low stress silicon dioxide.

4. The test device of claim 1, wherein said probe points have a size less than 5 mils on a side and less than 10 mils in height.

5. The test device of claim 1, wherein the number of probe points is at least one thousand.

6. The test device of claim 1, wherein the probe points each have a diameter of about 2 to 4 microns.

7. The test device of claim 1, wherein the probe points each have a diameter of about 2 to 4 mils.

8. The test device of claim 1, further comprising logic circuitry for providing said diagnostic signals to the probe points, said logic circuitry being formed on the flexible tester surface.

9. The test device of claim 1, wherein the probe points are located at both a central portion and a peripheral portion of said flexible tester surface.

10. The device of claim 1, wherein the probe points are capable of electrically contacting each transistor in a portion of the integrated circuit.

11. A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising:

a support for a wafer to be tested, said wafer having integrated circuit logic units including electrical devices and circuitry and contact points formed thereon;

a flexible tester surface having at least one thousand probe points corresponding to said contact points of said wafer;

means for electrically interconnecting said probe points of said flexible tester surface and said contact points of said wafer; and

means for supplying programmable input/output diagnostic signals to said flexible tester surface for testing the electrical devices and circuitry of said wafer.

12. A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising:

a support for a wafer to be tested, said wafer having integrated circuit logic units including electrical devices and circuitry and contact points formed thereon;

a flexible tester surface, said flexible tester surface having a number of probe points corresponding to said contact points of said wafer, wherein each probe point has a diameter not greater than four microns;

means for electrically interconnecting said probe points of said flexible tester surface and said contact points of said wafer; and

means for supplying programmable input/output diagnostic signals to said flexible tester surface for testing the electrical devices and circuitry of said wafer.

13. A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising:

a support for a wafer to be tested, said wafer having integrated circuit logic units including electrical devices and circuitry and contact points formed thereon;

a flexible tester surface having a number of probe points corresponding to said contact points of said wafer;

means for electrically interconnecting said probe points of said flexible tester surface and said contact points of said wafer;

programmable input/output circuitry formed on the flexible tester surface for supplying diagnostic signals to each of said probe points for testing the electrical devices and circuitry of said wafer.

14. A test device for testing the logic units of an integrated circuit formed on a semiconductor wafer comprising:

a support for a wafer to be tested, said wafer having integrated circuit logic units including electrical devices and circuitry and contact points formed thereon;

a tester surface disposed on said support, said tester surface having a number of probe points corresponding to said contact points of said wafer;

means for electrically interconnecting said probe points of said tester means and said contact points of said wafer;

means for supplying programmable input/output diagnostic signals to said tester surface for testing the electrical devices and circuitry of said wafer; and

interconnect circuitry formed on the tester surface for connecting the means for supplying to said probe points and including at least two conductive layers separated by an insulating layer.