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Planar vertical channel DMOS structure

DC
  • US 5,034,785 A
  • Filed: 08/24/1988
  • Issued: 07/23/1991
  • Est. Priority Date: 03/24/1986
  • Status: Expired due to Term
First Claim
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1. A vertical gate semiconductor device comprising:

  • a drain region of a first conductivity type;

    a body region of a second conductivity type opposite said first conductivity type overlaying said drain region, said body region having a first portion and a second portion, said second portion having a first top surface;

    a source region of said first conductivity type overlaying said first portion of said body region and having a second top surface substantially coplanar with said first top surface, said source region being separated from said drain region by said body region;

    a first dielectric region defining a groove extending downward through said source and said body regions and into said drain region;

    a gate region disposed in said groove and having a top surface depressed with respect to said second top surface of said source region, said gate region filling said groove at least up to a bottom of said source region;

    a second dielectric region having a substantially planar top surface overlaying said gate region, the top surface of said second dielectric region being substantially coplanar with said first and second top surfaces; and

    an electrically conductive region electrically contacting said source and body regions.

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