Multiprocessor intelligent cell for a network which provides sensing, bidirectional communications and control

• US 5,034,882 A
• Filed: 10/01/1990
• Issued: 07/23/1991
• Est. Priority Date: 11/10/1987
• Status: Expired due to Term

• Current Assignee: Echelon Corporation (Renesas Electronics Corporation)
• Original Assignee: Echelon Corporation (Renesas Electronics Corporation)
• Inventors: Smith, Stephen R., Eisenhard, Bruce T., Sander, Wendell B.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Kriess, Kevin A.
• Application Number:
  US07/593,330
• Time in Patent Office: 295 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 712/30
• CPC Class Codes: G06F 15/173 using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake

Abstract

A processor is described which is particularly useful in a cell which cell forms part of a network for sensing, communicating and controlling. The processor includes a plurality of sets of registers, each associated with a different processor. Each set of registers shares a single ALU. Data associated with each set of registers is simultaneously moved through a path which includes the registers, ALU, and memory.

Claims

1. A cell for use in a network that provides sensing, communication, and control, comprising:

(A) input and output means coupled to the network for providing communication with the network;

(B) a memory;

(C) a multiprocessor coupled to the input and output means for simultaneously performing a plurality of processes, wherein the multiprocessor comprises

(1) an arithmetic logic unit;

(2) a plurality of sets of registers, wherein each of the sets of registers is associated with one of the processes, wherein each of the sets of registers is coupled to the arithmetic logic unit, the sets of registers, and the memory, and wherein each set of registers includes

(a) an instruction register for storing an instruction; and

(b) logic means coupled to the instruction register for interpreting the instruction stored in the instruction register;

(3) control means coupled to the sets of registers, the arithmetic logic unit, and the memory for providing control signals for causing an output from one set of the registers to be provided as an input to the arithmetic logic unit for a first one of the processes while simultaneously causing an output of the arithmetic logic unit to be provided as an input to the memory for a second one of the processes while simultaneously causing an output of the memory to be provided as an input to another one of the sets of the registers for a third one of the processes.

2. The cell of claim 1, wherein the output of the arithmetic logic unit is selectively coupled to the input and output means.

3. The cell of claim 1, wherein the arithmetic logic unit comprises a first arithmetic logic unit for providing addresses for the memory and a second arithmetic logic unit for manipulating data.

4. The cell of claim 1, wherein the memory comprises a read-only memory, a random-access memory, and an electrically-programmable and electrically-erasable memory.

5. The cell of claim 1, wherein the arithmetic logic unit includes hardware means for converting four-bit nibbles into three-of-six code segments, wherein each segment includes three binary ones and three binary zeroes.

6. The cell of claim 1, wherein the control means comprise:

(A) a plurality of counters associated with the instruction registers;

(B) circuit means for providing initial settings to the counters, wherein the circuit means are coupled to receive the instructions stored in the instruction registers;

(C) a logic array coupled to receive as an input the contents of the counters and the instructions stored in the instruction registers; and

(D) delay means for delaying a plurality of outputs from the logic array, wherein outputs of the logic array and the delay means comprise control signals.

7. The cell of claim 6, further comprising clocking means for causing the counters to be clocked for minor instruction cycles.

8. The cell of claim 6, wherein the circuit means comprise a second logic array that receives the instructions as inputs, wherein the outputs of the second logic array are the initial settings, and wherein each initial setting represents the number of cycles needed to carry out a respective instruction.

9. The cell of claim 6, wherein the delay means comprise a plurality of registers.

10. A cell for use in a communication and control network, comprising:

(A) input and output means coupled to the network for providing one of the functions of sensing, communicating, and controlling;

(B) a memory;

(C) a plurality of processors for simultaneously performing a plurality of processes, wherein the plurality are coupled to the memory and to the input and output means, wherein the plurality of processors comprise;

(1) an arithmetic logic unit shared by the processors and

(2) a plurality of register groups, wherein each register group is associated with a respective processor, wherein outputs from the register groups are coupled to the arithmetic logic unit, wherein an output of the arithmetic logic unit is coupled to the memory, and wherein an output of the memory is coupled as an input to the register groups, and wherein each of the register groups comprises

(a) a base pointer register for storing a memory base pointer for a respective processor;

(b) an instruction pointer register for storing a memory pointer that points to an instruction for a respective processor;

(c) an instruction register for storing an instruction for a respective processor;

(d) a stack pointer register for storing a memory stack pointer for a respective processor;

(e) a return pointer register for storing a memory return pointer for a respective processor;

(3) control means for providing control signals for simultaneously transferring data from one of the register groups to the arithmetic logic unit while simultaneously transferring data associated with another one of the register groups from the arithmetic logic unit to the memory while simultaneously transferring data associated with another one of the register groups from the memory, wherein the control means are coupled to the register groups, wherein the control means comprise;

(a) a plurality of counters associated with the instruction registers;

(b) circuit means for providing initial settings to the counters, wherein the circuit means are coupled to receive the instructions stored in the instruction registers;

(c) a logic array coupled to receive as inputs the contents of the counters and instructions stored in the instruction registers;

(d) delay means for delaying a plurality of outputs from the logic array, wherein outputs of the logic array and the delay means comprise the control signals.

11. The cell of claim 10, further comprising clocking means for causing the counters to be clocked for minor instruction cycles.

12. The cell of claim 10, wherein each of the register groups is coupled to the input and output means, and each of the register groups independently communicates with the input and output means.

13. The cell of claim 10, wherein the circuit means comprise a second logic array that receives the instructions as inputs, wherein the outputs of the second logic array are the initial settings, and wherein each initial setting represents that number of cycles needed to carry out a respective instruction.

14. The cell of claim 10, wherein the delay means comprise a plurality of registers.

15. The cell of claim 10, wherein the arithmetic unit shifts a nibble left or right when at least one of the instruction registers contains a predetermined instruction.

16. The cell of claim 10, further comprising a direct signal path between each of the instruction pointer registers and the arithmetic logic unit.

17. The cell of claim 10, wherein the memory includes a read-only memory, a random-access memory, and an electrically programmable memory.

18. A multiprocessor having N processors, wherein N is an integer greater than one, comprising:

(A) N sets of register means for storing data, wherein each set of register means includes an instruction means for storing an instruction, and wherein each of the N sets of registers is associated with one of a plurality of processes;

(B) an arithmetic logic unit coupled to the N sets of register means, wherein an output from the sets of register means is provided as an input to the arithmetic logic unit;

(C) a memory coupled to the sets of register means and to the arithmetic logic unit;

(D) control means coupled to the N sets of registers, the arithmetic logic unit, and the memory for providing control signals for causing an output from one set of the register means to be provided as an input to the arithmetic logic unit for a first process of the plurality of processes while simultaneously causing an output from the arithmetic logic unit to be provided as an input to the memory for a second process of the plurality of processes while simultaneously causing an output from the memory to be provided as an input to another set of the register means for a third process of the plurality of processes, wherein the control means comprise

(a) a plurality of counters associated with the instruction registers,

(b) circuit means for providing initial settings to the counters, wherein the circuit means are coupled to receive the instructions stored in the instruction registers;

(c) a logic array coupled to receive as an input the contents of the counters and the instructions stored in the instruction registers;

(d) delay means for delaying a plurality of outputs from the logic array, wherein outputs of the logic array and the delay means comprise the control signals.

19. The multiprocessor of claim 18, wherein each initial setting of the initial settings of the counters represents the number of cycles needed to carry out a respective instruction stored in a respective instruction means.

20. The multiprocessor of claim 18, wherein the initial settings of the counters are sequentially provided as inputs to the logic array.

21. The multiprocessor of claim 18, wherein the instructions stored in the instruction means are sequentially provided as inputs to the logic array.

22. The multiprocessor of claim 18, wherein the circuit means comprise a second logic array that receives the instructions as inputs, and wherein the outputs of the second logic array are the initial settings.

23. The multiprocessor of claim 18, wherein the delay means comprise a plurality of registers.

24. The multiprocessor of claim 18, wherein the arithmetic logic unit comprises an address arithmetic logic unit and a data arithmetic logic unit.

25. The multiprocessor of claim 18, wherein the input to the logic array changes as one of the counters is clocked, thereby providing minor instruction cycles.

26. The multiprocessor of claim 18, wherein the arithmetic logic unit includes means (A) for converting six-bit segments of three-of-six codes into four-bit nibbles, wherein each segment comprises three binary ones and three binary zeroes, and (B) for converting four-bit nibbles into six-bit segments of three-of-six codes.