Cache memory device with fast data-write capacity

• US 5,034,885 A
• Filed: 03/10/1989
• Issued: 07/23/1991
• Est. Priority Date: 03/15/1988
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Aikawa, Takeshi, Maeda, Kenichi, Matoba, Tsukasa, Okamura, Mitsuyoshi
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): KULIK, PAUL V
• Application Number:
  US07/321,398
• Time in Patent Office: 865 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/143
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence

Abstract

A copy-back type cache memory device using a delayed wait method capable of completing a data-write process in one process cycle. The device includes single word memory means for storing the single word of the selected data in a data memory means when an access for a data-write is made, the single word being located at the address in the data memory means corresponding to the processor address; and copy-back memory means for restoring the superseded data along with other data together with which the superseded data forms a block, so that the block can be reorganized in its original state before the data-write process takes place. The device may alternatively include an address latch means for delaying transmission of a processor address from the processor to the data memory means by a predetermined number of process cycles when access by the processor is for a data-write process; and a data latch means for delaying transmission of a processor data from the processor to the data memory means by the predetermined number of process cycles when access by the processor is for a data-write process.

Claims

1. A cache memory device to be placed between a processor and a main memory in a computer, comprising:

data memory means for storing selected data stored in said main memory, one of said selected data in said data memory means, which is located at an address in said data memory means corresponding to a processor address to which said processor is making an access, being superseded as a superseded one of said selected data by one of processor data from said processor at a particular process cycle when said access by said processor is for a data-write process, and a group of a plurality of data among said selected data being stored as a block of data in said data memory means;

hit/miss detector means for determining, at said particular process cycle, said access as a hit when said access is made with respect to a correct address in said data memory means, and as a miss otherwise;

means for memorizing said superseded one of said selected data at said address in said data memory means corresponding to said processor address when said access for said data-write process is made;

copy-back memory means for storing one block of data which contained said superseded one of said selected data in said data memory means in an original state before said data-write process took place; and

selector means for selecting said superseded one of said selected data memorized in said means for memorizing as an input, corresponding to said processor address, to said copy-back memory means at another process cycle later than said particular process cycle only when said access was determined as a miss, such that said one block in said original state before said data-write process is reconstructed in said copy-back memory means.

2. The device of claim 1, wherein said hit/miss detector means includes:

tag memory means for storing addresses of said selected data stored in said main memory; and

means for comparing said processor address with said addresses in said tag memory means, and for determining said access as a hit when one of said addresses in said tag memory means coincides with said processor address, and as a miss otherwise.

3. The device of claim 1, further comprising restoration buffer means connecting said data memory means and said means for memorizing, for restoring data in said means for memorizing into an address in said data memory means corresponding to said processor address when said access by said processor is for a non-cache data-write process.

4. The device of claim 1, wherein a data-read process is carried out in a delayed-wait method such that said data-read process can be completed in one process cycle.