Computer system including a page mode memory with decreased access time and method of operation thereof

• US 5,034,917 A
• Filed: 05/26/1988
• Issued: 07/23/1991
• Est. Priority Date: 05/26/1988
• Status: Expired due to Fees

• Current Assignee: Lenovo Singapore Pte Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: Bland, Patrick M., Dean, Mark E.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Kriess, Kevin A.
• Application Number:
  US07/196,721
• Time in Patent Office: 1,153 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 365/203, 365/235
• US Class Current: 711/167
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/362 with centralised access control
• CPC Class Codes: G06F 8/20 Software design
• CPC Class Codes: G06F 8/71 Version control security arrangements therefor G06F21/57; Configuration management
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address

Abstract

A computer system is provided in which memory access time is substantially reduced. After row address strobe (RAS) and column address strobe (CAS) signals are used to select a particular address in a memory during a first memory cycle, the addressed data is latched for later transfer to a data bus. A CAS precharge of the memory is then conducted after such latching and prior to the end of the first memory cycle before the commencement of the second memory cycle.

Claims

1. A computer system comprising:

a page mode memory having an address bus and a data bus coupled thereto;

processing means, coupled to said address bus and said data bus, for processing data in said system and for providing said memory with a first address signal during a first memory cycle, said first address signal corresponding to a location in memory of data to be accessed;

first control means, coupled to said memory, for supplying said memory with a row address strobe (RAS) signal during said first memory cycle;

second control means, coupled to said emory, for supplying a column address strobe (CAS) signal to said memory during said first memory cycle and subsequent to said RAS signal;

latching means, coupled between said memory and said data bus, for latching the data thus addressed for later transfer on said data bus;

CAS precharge means, coupled to said memory, for subjecting said memory to a CAS precharge subsequent to said latching means latching said data and prior to the end of said first memory cycle.

2. The computer system of claim 1 wherein said system further comprises means for providing said memory with a second address signal corresponding to data in memory to be accessed during a second memory cycle subsequent to said first memory cycle, said second address signal being provided to said memory prior to the end of said first memory cycle.

3. In a computer system including a page mode memory having an address bus and a data bus coupled thereto and further having first, second a subsequent memory cycles associated therewith, a method for reading information stored in said memory comprising the steps of:

providing to said memory an address signal corresponding to the location of data to be accessed in said memory;

supplying said memory with a row address strobe (RAS) signal during said first memory cycle;

applying a column address strobe (CAS) signal to said memory during said first memory cycle and subsequent to said RAS signal;

latching the data thus addressed for later transfer on said data bus;

performing a CAS precharge on said memory subsequent to said latching step and prior to the end of said first memory cycle.

4. In a computer system including a processor coupled to a page mode memory via an address bus and a data bus and further having first, second and subsequent memory cycles associated therewith, a method for transferring data from said memory to said processor while avoiding the addition of wait states, said data being stored in said memory in rows and columns, said method comprising the steps of:

providing to said memory the address of a row in which data to be accessed is located;

supplying to said memory a row address probe (RAS) signal during said first memory cycle;

providing to said memory the address of a column in which the data to be accessed is located, this step occurring in time during said first memory cycle and subsequent to said supplying of said RAS signal;

applying a column address strobe (CAS) signal to said memory during said first memory cycle to complete the addressing of said data;

latching the data thus addressed for later transfer on said data bus, and

performing a CAS precharge on said memory subsequent to said latching step and prior to the end of said first memory cycle.

5. In a computer system including a page mode memory for storing data wherein a first access of a page of memory occurs during a current memory cycle and a second access of said page of memory occurs during a next memory cycle, said second access having a CAS precharge associated therewith, a method of memory control comprising:

latching, prior to CAS precharge, data from said first access to preserve the data for later transfer, and

advancing the CAS precharge associated with said second access from said next memory cycle into said current memory cycle.