Adaptive associative memory comprising synapes of CMOS transistors

• US 5,034,918 A
• Filed: 02/01/1990
• Issued: 07/23/1991
• Est. Priority Date: 02/02/1989
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeong, Ho-sun
• Primary Examiner(s): Popek, Joseph A.
• Assistant Examiner(s): Whitfield, Michael A.
• Application Number:
  US07/473,465
• Time in Patent Office: 537 Days
• Field of Search: 364/807, 364/513, 365/49, 307/201, 307/202, 307/570, 307/584
• US Class Current: 365/49.1
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

An associative memory for storing an n-bit stored vector in m different states comprises n first amplifiers connected between n input terminals and n output terminals, and m second amplifiers to feedback to the input side the designated states of the stored vectors. Synapses of the storing unit store the above mentioned stored vectors in the a binary 1 or 0; synapses of the label units couple the respective intersections between the input and output lines of the second amplifiers; and synapses of the vector units couple the intersections between the output lines of the first amplifiers and the input lines of the second amplifiers. According to the present invention, the outputs of the amplifiers are stabilized, so that stabilized operations can be obtained.

Claims

1. An associative memory comprising:

n first input lines for receiving an n-bit input vector;

n first amplifiers for amplifying each bit of the n-bit input vector, said in first amplifiers corresponding to ones of said in first input lines;

n first output lines for corresponding ones of said n first amplifiers;

m second amplifiers;

m second input lines for corresponding ones of said m second amplifiers, said m second input lines forming first intersections with said n first output lines;

m n-bit stored vectors formed at said first intersection;

storing unit synapses of a plurality of PMOS transistors disposed at predetermined ones of said first intersections corresponding to binary components "1" of the m n-bit stored vectors, said plurality PMOS transistors having predetermined conductance values and coupling a first power source voltage to said m second input lines in accordance with an output of said n first amplifiers on said n first output lines;

m second output lines for corresponding ones of said second amplifiers, said m second output lines forming second intersections with said second input lines;

label unit synapses of a plurality of NMOS transistors disposed at predetermined ones of said second intersections, whereby the output of one of said m second amplifiers is operatively fedback to each of said n first input lines corresponding to the other of said m second amplifiers;

said plurality of NMOS transistors having a conductance value of "1" and coupling a second power source voltage to said second input lines in accordance with outputs of said m second amplifiers on said m second output lines;

said conductance values of respective said ones of plurality of PMOS transistors of said storing unit synapses being one less than the sum of the conductance values of said plurality of NMOS transistors of said label unit synapses coupled to the corresponding ones of said m second input lines;

said m second output lines of said m second amplifiers forming third intersections with said n first input lines of said n first amplifiers;

vector unit synapses having a plurality of NMOS transistors and PMOS transistors, said plurality of PMOS transistors being disposed at predetermined ones of said third intersections corresponding to said first intersections wherein said plurality of PMOS transistors of said storing unit synapses are disposed;

said plurality of NMOS transistors being disposed at the other of said third intersections and having a conductance value of "1" , said plurality of NMOS transistors coupling the second power source voltage to said n first input lines of said n first amplifiers in accordance with the outputs of said m second amplifiers on said m second output lines; and

said plurality of PMOS transistors of said vector unit synapses having conductance values equal to the number of NMOS transistors coupled to the corresponding ones of said n first input lines, said plurality of PMOS transistors coupling the first power source voltage to said n first input lines of said n first amplifiers in accordance with the outputs of said m second amplifiers on said m second output lines.

2. An associative memory as claimed in claim 1, wherein the m n-bit stored vectors maintain a bit distance of Dt≧

2t+1, where t represents a number of bits to be corrected, and Dt represents a number of checked bits.

3. An associative memory as claimed in claim 1, wherein each of said n first and m second amplifiers comprises two serially connected CMOS inverters.

4. An associative memory as claimed in claim 1, wherein said associative memory further comprises n transmitting gates for transmitting said n-bit input vector to said n first input lines of said n first amplifiers in response to a clock signal.

5. An associative memory as claimed in claim 1, wherein said first power source voltage is a supply voltage VDD and said second power source voltage is a ground potential GND.