Semiconductor memory device having two-dimensional matrix array

• US 5,034,928 A
• Filed: 07/21/1989
• Issued: 07/23/1991
• Est. Priority Date: 07/22/1988
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Isobe, Mitsuo
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/383,212
• Time in Patent Office: 732 Days
• Field of Search: 365/230.03, 365/230.06
• US Class Current: 365/230.03
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A semiconductor memory device has a memory cell matrix in which a plurality of memory cells are connected in rows by work lines and in columns by bit lines. The device comprises cell row groups each of which is formed by memory cell rows commonly activated by several row address signals at a first selection stage, a row group selection decoder having the smallest decoding circuits as a first stage decoder each connected to the row group(s) by first stage word line and commonly activating any group(s) at the first row selection stage by several row address signals, and a row selection decoder as a second stage decoder having the smallest decoding units entirely provided in the matrix and each activating any cell row(s) at a second selection stage by remaining row address signals.

Claims

1. A semiconductor memory device having a memory cell matrix in which a plurality of memory cells are connected in rows by word lines and in columns by bit lines, a row selection decoder for activating an arbitrary cell row by a row address signal, and a column selection decoder for selecting desired cell arranged in a desired cell row activated by said row selection decoder so as to access a specified memory cell, the memory device comprising:

first row-address signal lines provided along one side of said memory cell matrix having a rectangular shape and for supplying a first row address signal to a cell group row selector;

said cell group row selector having a plural number of decoder circuits, one of which is selected by said first row address signal;

a plural number of cell row groups, each connected to a corresponding decoder circuit by a corresponding first word line and being activated by a cell group row activation signal from said decoder circuit when that decoder circuit is selected;

each cell row group having a plural number of cell groups having a plural number of cell rows;

second row-address signal lines positioned inside a boundary line of an area treated as said memory matrix and connected to a plural number of decoders symmetrically arranged in each cell group connected vertically by the second row-address signal line; and

said cell rows symmetrically connected to corresponding decoders by corresponding second word lines and activated by cell row activation signals from corresponding decoders when those corresponding decoders are activated.

2. A memory device according to claim 1 wherein said cell row groups have respectively two memory cell rows, in each of which a plurality of said memory cells are connected by said second word line receiving a row selection signal from a decoder circuit on the basis of said second row address signals through the lines.

3. A memory device according to claim 1 wherein said cell row groups have respectively four memory cell rows, in each of which a plurality of said memory cells are connected by said second word line receiving a second row selection signal by a decoder circuit on the basis of said second row address signals through the lines.

4. A memory device according to claim 1, further comprising first and second stage decoders, wherein said first stage decoder activates any first stage word line so as to select one or more row group or groups and, then said row selection decoder as a said second stage decoder activates any second stage word line and/or lines so as to select one or more cell row or rows.

5. A memory device according to claim 1, further comprising a first and second stage decoders, wherein said first stage decoder selects one first word line at a first word line selection stage and then, said second stage decoder selects one or more cell row of rows among a plurality of said cell rows in one or more row group of groups.

6. A memory device according to claim 1, wherein at least said memory cell matrix is constructed in one chip, and said row selection decoder is also constructed in said memory cell matrix.

7. A memory device according to claim 6, wherein said row selection decoder has a plurality of said decoder circuits which are provided in said memory cell matrix along both sides of several row address signal lines for supplying remaining row address signals.