N:1 time-voltage matrix encoded I/O transmission system

• US 5,034,964 A
• Filed: 11/08/1988
• Issued: 07/23/1991
• Est. Priority Date: 11/08/1988
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Tandem Computers Incorporated (HP Inc.)
• Inventors: Horst, Robert, Khan, Aurangzeb K., Yue, Lordson L.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Bocure, Tesfaldet
• Application Number:
  US07/268,423
• Time in Patent Office: 987 Days
• Field of Search: 375/17, 375/24, 375/25, 375/20, 358/426, 370/37, 370/112, 370/116, 370/114, 341/56, 340/825.77, 328/62, 307/243
• US Class Current: 375/242
• CPC Class Codes: G05F 1/577 for plural loads
• CPC Class Codes: G05F 3/22 wherein the transistors are of the bipolar type only G05F3/26, G05F3/30 take precedence
• CPC Class Codes: H04L 5/02 Channels characterised by the type of signal

Abstract

Encoding and decoding circuits are described for functioning as both a time and voltage based transmission system. Multiple binary inputs can be transmitted and received on a single I/O pin by encoder and decoder circuits using high speed emitter coupled-like logic.

Claims

1. A transmission system for transmitting N, N being an integer, binary input voltage signals, each having a magnitude equal to either a first or a second voltage level and received on N input signal ports, out of a single output port, said system comprising:

a clock generating for setting the states of a plurality of clock signals to define a set of M, M being a fixed integer less than N, sequential time slots; and

a time/voltage concurrent encoder, adapted to receive said N binary signals and said clock signals, for selecting a distinct subset of N/M of said binary input signals and concurrently converting said selected N/M binary signals into a corresponding one of 2**(N/M) discrete predetermined voltage levels during each time slot, with the corresponding voltage level uniquely encoding the values of the selected N/M binary input signals so that the encoded values of said N binary input signals are transmitted out of the single output port during said M sequential time slots.

2. The invention of claim 1 wherein said encoder comprises:

a set of M single stage multi-level encoders, each single stage encoder coupled to receive a unique subset of N/M binary input signals associated with a unique corresponding time slot, with each single stage encoder selected during the corresponding time slot, and with each single stage encoder for encoding the (M/N) received binary signals into a corresponding one of said 2**(N/M) discrete predetermined voltage levels when selected.

3. The invention of claim 2 wherein said single stage encoder is implemented as an emitter-coupled logic-type circuit that conducts current from a VCC terminal to a VEE terminal and where said circuit receives a reference voltage having a value between the high and low binary voltage values, the encoder comprising:

a first resistor coupling a first collector ANDed output node to VCC;

a second resistor coupling a second collector ANDed output node to VCC;

and wherein each single stage encoder comprises;

N/M emitter-coupled comparators, all having current inputs coupled to said first and second nodes and each having a current output coupled to VEE through an associated current source providing an associated fixed magnitude of current, with each emitter-coupled comparator having a first logic input coupled to an associated one of said N/M binary signals and every emitter-coupled comparator having a second logical input tied to the reference voltage, and with each emitter-coupled comparator for steering its associated fixed amount of current through said first node if its associated binary signal is in a first state and through said second node if said associated binary signal is in a second state so that the value of the discrete voltage level on said first node uniquely encodes the binary values of said N/M binary signals.

4. The invention of claim 3 wherein the discrete voltage levels at said second node vary inversely as the discrete voltage levels at node 1 and further comprising:

a pull-up transistor having a first terminal coupled to said VCC terminal, a base terminal coupled to said first node, and a second terminal coupled to an output port, said pull-up transistor for conducting current from said VCC terminal to said output port;

a pull-down transistor having a first terminal coupled to said output port, a base terminal coupled to said VEE terminal via a control resistor, and a second terminal coupled to said VEE terminal, said pull-down transistor for conducting current from said output terminal to said VEE terminal;

a pull-down control transistor having a first terminal coupled to said VCC terminal, a base terminal coupled to said second node, and a second terminal coupled to said base terminal of said pull-down transistor via a current supply resistor; and

a control resistor coupling said base of said pull-down transistor and said current supply resistor to said VEE terminal.

5. A time-voltage decoder comprising:

a voltage level generator for generating (2**X)-1 ordered voltage levels to partition a predetermined voltage interval into 2**X subintervals;

a non-binary converter, adapted to receive an input voltage signal having an amplitude equal to one level in a set of 2**X predetermined discrete voltage levels, with each discrete voltage level included in an associated one of said subintervals and uniquely encoding the values of a set of X binary signals, said non-binary converter for converting said received input voltage signal into X decoded binary output signals;

a clock generator for setting the states of a plurality of clock signals to define a set of M, M being a fixed integer, sequential time slots;

a data latch network, having an ordered set of N output ports, N being an integer equal to the product of M multiplied by X and adapted to receive said clock signals and said decoded binary output signals, with said N output ports partitioned into M subsets of X output ports and each subset associated with a given time slot, said network for latching said X decoded binary output signals received during the given time slot onto the X output ports of the subset associated with the given time slot.

6. The invention of claim 5 wherein N is 8 and the reference voltage levels are VR1, VR2, VR3 with VR3 having the most negative voltage, with said decoder implemented in an emitter-coupled logic-like (ECL) circuit that conducts current from a VCC terminal to a VEE terminal and comprises:

a first emitter-coupled comparator having a first logic input coupled to said input voltage signal and a second logic input coupled to VR1;

a second emitter-coupled comparator having a first logic input coupled to said input voltage signal and a second logic input coupled to VR2;

a third emitter-coupled comparator having a first logic input coupled to said input voltage signal and a second logic input coupled to VR3;

a first logic circuit, having an input coupled to the output terminal of the said second comparator, for setting the value of a first decoded output signal to a first binary state only if the magnitude of said input voltage signal is greater than VR2;

a second logic circuit, having inputs coupled to the outputs of the said first, second, and third comparators, for setting the value of a second decoded output signal to said first binary state only if the magnitude of said input voltage signal is greater than VR1 or in the interval from VR2 to VR3.

7. A transmission system, of the type including a system clock signal for defining system clock cycles, for transmitting N, N being an integer, binary input signals each characterized by a first or a second state, through a single output port, said system comprising:

a time slot generator, adapted to receive said system clock signal, for setting the states of a plurality of clocking signals to define a set of M, M being a fixed integer, sequential time slots during each system clock cycle;

a time/voltage concurrent encoder, adapted to receive said N binary signals and said clock signals, for dividing said N binary signals into M time slots, generating a distinct subset of N/M of said binary input signals and concurrently converting the said selected binary input signals into a corresponding one of 2**(N/M) discrete predetermined voltage levels during each time slot, with the corresponding voltage level uniquely encoding the values of the selected N/M binary signals;

a voltage level generator for generating (2**(N/M)-1 ordered voltage levels to partition a predetermined voltage interval into 2**(N/M) subintervals;

a non-binary converter, adapted to receive an input voltage signal having an amplitude equal to one level in a set of 2**(N/M) predetermined discrete voltage levels, with each discrete voltage level included in an associated one of said subintervals and uniquely encoding the values of a set of N/M binary signals, said non-binary converter for converting said received input voltage signal into N/M decoded binary output signals, each corresponding to one of said N/M binary signals encoded by said received input signal.

8. In a multi-level logic system of the type that generates discrete voltage levels on a first node and complementary discrete voltage levels on a second node, an output buffer for providing dynamic pull-down to reduce output slew for large signal deltas, said system comprising:

a pull-up transistor having a first terminal coupled to said VCC terminal, a base terminal coupled to said first node, and a second terminal coupled to an output port, said pull-up transistor for conducting current from said VCC terminal to said output port;

a pull-down transistor having a first terminal coupled to said output port, a base terminal coupled to said VEE terminal via a control resistor, and a second terminal coupled to said VEE terminal, said pull-down terminal for conducting current from said output terminal to said VEE terminal;

a pull-down control transistor having a first terminal coupled to said VCC terminal, a base terminal coupled to said second node, and a second terminal coupled to said base terminal of said pull-down transistor via a current supply resistor; and

a control resistor coupling said base of said pull-down transistor and said current supply resistor to said VEE terminal.