Method of using electronically reconfigurable logic circuits
First Claim
1. A method comprising the steps:
- providing first and second electrically reconfigurable logic circuits (ERCLCs);
providing first input data representative of a first digital logic network, said input data including primitives comprised of boolean logic gates, and nets interconnecting said primitives;
automatically partitioning said first input data into first and second portions;
providing the first portion of the partitioned first data to the first ERCLC so a first portion of the first digital logic network represented thereby takes actual operating form on the first ERCLC;
providing the second portion of the partitioned first data to the second ERCLC so a second portion of the first digital logic network represented thereby takes actual operating form on the second ERCLC;
interconnecting the first and second ERCLCs so that at least one net specified in the first input data extends between the first and second ERCLCs;
providing second input data representative of a second digital logic network entirely unrelated to the first digital logic network except that both include primitives comprised of boolean logic gates, and nets interconnecting said primitives, and both are to take actual operating form on the same ERCLCs;
automatically partitioning said second input data into first and second portions;
providing the first portion of the partitioned second data to the first ERCLC so a first portion of the second digital logic network represented thereby takes actual operating form on the first ERCLC;
providing the second portion of the partitioned second data to the second ERCLC so a second portion of the second digital logic network represented thereby takes actual operating form on the second ERCLC;
interconnecting the first and second ERCLCs so that at least one net specified in the second input data extends between the first and second ERCLCs.
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Abstract
A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.
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Citations
19 Claims
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1. A method comprising the steps:
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providing first and second electrically reconfigurable logic circuits (ERCLCs); providing first input data representative of a first digital logic network, said input data including primitives comprised of boolean logic gates, and nets interconnecting said primitives; automatically partitioning said first input data into first and second portions; providing the first portion of the partitioned first data to the first ERCLC so a first portion of the first digital logic network represented thereby takes actual operating form on the first ERCLC; providing the second portion of the partitioned first data to the second ERCLC so a second portion of the first digital logic network represented thereby takes actual operating form on the second ERCLC; interconnecting the first and second ERCLCs so that at least one net specified in the first input data extends between the first and second ERCLCs; providing second input data representative of a second digital logic network entirely unrelated to the first digital logic network except that both include primitives comprised of boolean logic gates, and nets interconnecting said primitives, and both are to take actual operating form on the same ERCLCs; automatically partitioning said second input data into first and second portions; providing the first portion of the partitioned second data to the first ERCLC so a first portion of the second digital logic network represented thereby takes actual operating form on the first ERCLC; providing the second portion of the partitioned second data to the second ERCLC so a second portion of the second digital logic network represented thereby takes actual operating form on the second ERCLC; interconnecting the first and second ERCLCs so that at least one net specified in the second input data extends between the first and second ERCLCs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification