Die attach using gold ribbon with gold/silicon eutectic alloy cladding

• US 5,037,778 A
• Filed: 05/12/1989
• Issued: 08/06/1991
• Est. Priority Date: 05/12/1989
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Whitcomb, Michael J., Stark, James
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Graybill, David E.
• Application Number:
  US07/351,863
• Time in Patent Office: 816 Days
• Field of Search: 437/214, 437/215, 437/216, 437/209, 148/DIG. 12, 148/DIG. 62, 357/67, 357/71, 228/209, 228/247, 228/245, 228/246, 228/263.11, 228/123, 29/831, 29/832, 174/52.5
• US Class Current: 228/121
• CPC Class Codes: H01L 2224/29076 being mutually engaged together, e.g. through inserts
• CPC Class Codes: H01L 2224/83101 as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/832 Applying energy for connecting
• CPC Class Codes: H01L 2224/83805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/83825 Solid-liquid interdiffusion
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/0132 Binary Alloys
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/351 Thermal stress
• CPC Class Codes: H01L 2924/3512 Cracking
• CPC Class Codes: Y10S 148/012 : Bonding, e.g. electrostatic for strain gauges
• CPC Class Codes: Y10S 148/062 : Gold diffusion
• CPC Class Codes: Y10T 29/49144 : by metal fusion

Abstract

An improved method for eutectically bonding a silicon wafer into a cavity of a packaging body. A gold/silicon eutectic alloy cladding is formed on a ribbon made of gold. A strip is cut from the ribbon and placed into the package cavity with the cladding side up. Then a die is placed onto the strip on top of the gold/silicon cladding. The die is then scrubbed at a temperature of approximately 400° C. and the gold/silicon cladding acts as a catalyst to form a gold/silicon eutectic bond between the die and the packaging body.

Claims

1. A method for bonding a semiconductor die onto a dielectrically insulated body having a cavity for receiving the die, said cavity having a bottom onto which a layer of gold has been deposited, said die having a silicon chip onto which an intermediate metal barrier layer has been deposited, said method comprising the steps of:

(a) preheating the body and gold layer to a temperature of approximately 400°

C.;

(b) cutting a strip from a ribbon made of gold and having a gold/silicon eutectic alloy cladding on one side thereof;

(c) placing said strip into said cavity onto said gold layer such that said cladding is opposed from said gold layer;

(d) placing said die onto said strip such that said intermediate metal layer is adjacent to said cladding;

(e) heating said body, strip and die combination to a temperature of approximately 400°

C.;

(f) scrubbing said die on said ribbon and cladding at a bonding temperature of approimately 400°

C. such that said cladding melts and forms a liquid layer which acts as a catalyst for further transfer of thermal energy from said gold ribbon and said gold layer to said die;

wherein continued scrubbing of said die causes silicon atoms from said chip to penetrate said intermediate barrier metal layer and combine with said gold/silicon liquid layer, thereby increasing the percentage of silicon relative to the percentage of gold in said liquid layer and causing the melting point of said gold/silicon layer to decrease.

2. The method defined by claim 1 wherein said scrubbing is initiated at a melting point of said gold/silicon eutectic alloy having an initial value greater than the minimum melting temperature of the gold/silicon eutectic alloy, but continued scrubbing causes said eutectic melting point to decrease in value until said minimum value is reached, at which time further reaction of silicon from said chip increases the percentage of silicon in comparison to gold, causing said eutectic melting point to increase until said eutectic melting point reaches said bonding temperature, wherein silicon atoms in said die migrate across said intermediate metal barrier layer to said gold ribbon and form a gold/silicon eutectic bond.

5. The method as defined by claim 1 wherein the ratio of gold to gold/silicon eutectic alloy in said ribbon ranges between approximately 30 to 1 and 80 to 1.

6. The method as defined by claim 1 wherein said cladding is approximately centered upon said ribbon.

7. The method as defined by claim 1 wherein the surface area of said strip is at least 70% of the surface area of a surface of said die which is to contact said ribbon during said scrubbing step.

3. The method as defined in cliam 1, wherein said intermediate metal barrier layer is comprised of chromium and said bonding is substantially independent of the thickness of said intermediate metal barrier layer.

4. The method as defined in claim 3, wherein said die includes a gold layer deposited on said intermediate metal barrier layer, such that said gold layer makes contact with said gold/silicon eutectic alloy when said die is placed onto said strip.