Multiple-modulator fractional-N divider

• US 5,038,117 A
• Filed: 09/07/1990
• Issued: 08/06/1991
• Est. Priority Date: 01/23/1990
• Status: Expired due to Term

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Miller, Brian M.
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US07/579,469
• Time in Patent Office: 333 Days
• Field of Search: 331/1 A, 331/16, 331/18, 331/25, 375/120, 455/260
• US Class Current: 331/16
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

A fractional-N type frequency synthesizer includes a frequency divider having a selectable integer divide number which is periodically temporarily altered to provide an average rational divide number for the frequency divider. A number of modulator circuits coupled in cascade fashion provide a zero sum modulation signal which varies the value of the frequency divider divisor value such that the net change in divisor value due to the modulation signal is zero thereby reducing phase noise resulting from the temporary altering of the integer divisor value close to the frequency synthesizer carrier frequency.

Claims

1. A variable frequency synthesizer comprising:

a variable frequency oscillator for generating an output signal having a selectable output frequency which is a rational multiple of the frequency of a reference signal;

frequency divider means having an input coupled to the output of said variable frequency oscillator, said frequency divider means having a selectable variable integer divisor, said frequency divider means for producing an intermediate signal having a frequency equal to the frequency of the variable frequency output signal divided by said variable divisor value;

phase comparison means coupled to said frequency divider means for comparing the phase of said intermediate signal to the phase of a reference signal and generating an error signal indicative of a phase difference therebetween, said error signal coupled to a control input at said variable frequency oscillator;

first means coupled to an input of said frequency divider means, said first means responsive to a control signal representative of a fractional divisor value for generating a first modulation signal to periodically temporarily alter said integer divide value such that said frequency divider means has a predetermined average rational divisor value; and

second means coupled to an output of said first means and having an output coupled to said frequency divider means, said second means responsive to a first sum signal output by said first means for generating a second modulation signal varying the value of said integer divisor, the net change in said integer divisor value due to said second modulation signal being zero.

2. A frequency synthesizer as in claim 1 further comprising at least one additional means coupled to an output of said second means and responsive to a second sum signal output by said second means for generating a third modulation signal, said third modulation signal being coupled back to said second means and summed with said second modulation signal.

3. A frequency synthesizer as in claim 2 wherein said first means comprises an integrator means having an input for receiving said control signal, said integrator means responsive to said control signal for generating an overflow signal and said first sum signal.

4. A frequency synthesizer as in claim 3 further comprising summer means connected between said first integrator means and said frequency divider means, said summer means having a first input for receiving said overflow signal and a second input coupled to said second means for receiving said second modulation signal, said summer means generating said first modulation signal, said first modulation signal being the sum of said overflow signal and said second modulation signal.

5. A frequency synthesizer as in claim 4 wherein said second means and each said additional means comprises a modulator cell, each said modulator cell comprising:

clocked integrator means having an input port and first and second output ports;

summer means having an output port and first and second input ports, said first input port coupled to said integrator means first output port for receiving an overflow signal generated by said clocked integrator means; and

differentiator means having an input port and an output port, said differentiator means input port coupled to said summer means output port, said differentiator means responsive to a pulse at its input port for generating a first output pulse of identical polarity and a second output pulse of opposite polarity following said first output pulse; and

said modulator cells coupled together in cascade fashion, said integrator means second output port coupled to the next succeeding integrator means input port, said differentiator means output port coupled to said summer means input port of the immediately preceding modulator cell.

6. A frequency divider for dividing the frequency of an input signal by a selectable rational number comprising:

frequency divider means having an input for receiving an input signal, an output for outputting an output signal, the frequency of said output signal being the frequency of said input signal divided by a selectable rational number, said frequency divider means including a modulus control input for receiving a modulus control signal;

first means coupled to said modulus control input of said frequency divider means, said first means responsive to a control signal representative of a fractional divisor value for generating a first modulation signal for periodically temporarily altering an integer divide value such that said frequency divider means has a predetermined average rational divisor value; and

second means coupled to an output of said first means and having an output coupled to said frequency divider means, said second means responsive to a first signal output by said first means for generating a second modulation signal periodically varying the value of said integer divider value, the net change in said integer divisor value due to said second modulation signal being zero.

7. A frequency divider as in claim 6 further comprising at least one additional means coupled to an output of said second means and responsive to a second signal output by said second means for generating a third modulation signal, said third modulation signal coupled back to said second means and summed with said second modulation signal.

8. A frequency divider as in claim 6 wherein said first means comprises accumulator means having an input for receiving said control signal, said accumulator means responsive to said control signal for generating an overflow signal and a first sum signal.

9. A frequency divider as in claim 8 further comprising summer means connected between said first accumulator means and said frequency divider means, said summer means having a first input for receiving said overflow signal and a second input coupled to said second means for receiving said second modulation signal, said summer means generating said first modulation signal, said first modulation signal being the sum of said overflow signal and said second modulation signal.

10. A frequency divider as in claim 9 further comprising a plurality of modulation cells, said second means and each said modulation cell comprising:

accumulator means having an input port and first and second output ports;

summer means having an output port and first and second input ports, said first input port coupled to said accumulator means first output port for receiving an overflow generated by said accumulator means; and

differentiator means having an input port and an output port, said differentiator means input port coupled to said summer means output port said differentiator means responsive to a pulse at its input port for generating a first output pulse of identically plurality and a second output pulse of opposite plurality following said first input pulse; and

said modulator cells coupled together in cascade fashion, said accumulator second output port coupled to the next succeeding accumulator means input port, said differentiator means output port coupled to said summer means input port of the immediately proceeding modulator cell.