Circuit configuration for an integratable and controllable ring oscillator

• US 5,038,118 A
• Filed: 09/05/1990
• Issued: 08/06/1991
• Est. Priority Date: 09/05/1989
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Langenkamp, Ulrich
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US07/578,029
• Time in Patent Office: 335 Days
• Field of Search: 331/57, 331/108 B, 331/111, 331/135, 331/136, 331/177 R, 331/34
• US Class Current: 331/57
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/354 Astable circuits

Abstract

A circuit configuration of an integratable and controllable ring oscillator for generating a clock signal includes first and second stages being connected between supply terminals and having input and output terminals. The output terminal of the first stage is connected to the input terminal of the second stage. An inverter is connected between the output terminal of the second stage and the input terminal of the first stage. The input terminal of the second stage supplies a clock signal. Each of the stages includes first and second transistors having load paths connected between the supply terminals in a series circuit with a connecting point between the transistors. The second transistor has a gate terminal connected to the input terminal. The first transistor determines the frequency of the clock signal, is controllable in accordance with a control variable and acts as a current source. A capacitor has one terminal connected to the connecting point and another terminal connected to a fixed potential. A decoupling stage is connected between the output terminal and the connecting point.

Claims

1. Circuit configuration of an integratable and controllable ring oscillator for generating a clock signal, comprising:

first and second stages being connected between supply terminals and having input and output terminals, said output terminal of said first stage being connected to said input terminal of said second stage, an inverter connected between said output terminal of said second stage and said input terminal of said first stage, and said input terminal of said second stage supplying a clock signal;

each of said stages including first and second transistors having load paths connected between said supply terminals in a series circuit with a connecting point between said transistors, said second transistor having a gate terminal connected to said input terminal, said first transistor determining the frequency of the clock signal, being controllable in accordance with a control variable and acting as a current source, a capacitor having one terminal connected to said connecting point and another terminal connected to a fixed potential, and a decoupling stage connected between said output terminal and said connecting point.

2. Circuit configuration according to claim 1, wherein one of said supply terminals is to be applied to a positive potential and is connected to said second transistor and to said other terminal of said capacitor in each of the stages.

3. Circuit configuration according to claim 1, wherein in each of said stages, one of said supply terminals is to be applied to a positive potential and is connected to said second transistor, and the other of said supply terminals is to be applied to ground potential and is connected to said other terminal of said capacitor.

4. Circuit configuration according to claim 1, wherein each stage has a control input terminal acted upon by said control variable, and said first transistor of each stage has a gate terminal connected to said control input terminal.

5. Circuit configuration according to claim 4, wherein the control variable is a control current or control voltage.

6. Circuit configuration according to claim 1, wherein said decoupling stage has at least one inverter stage connected between said supply terminals.

7. Circuit configuration according to claim 1, including a control input terminal being acted upon by a variable dependent on a supply voltage of the ring oscillator, and a third transistor being connected parallel to said first transistor and having a gate terminal connected to said control input terminal.

8. Circuit configuration according to claim 4, including another control input terminal being acted upon by a variable dependent on a supply voltage of the ring oscillator, and a third transistor being connected parallel to said first transistor and having a gate terminal connected to said other control input terminal.

9. Circuit configuration according to claim 1, wherein said capacitor is an MOS transistor having a gate terminal forming one terminal of said capacitor and a short-circuited load path forming the other terminal of said capacitor.

10. Circuit configuration according to claim 1, wherein said transistors are NMOS transistors.

11. Circuit configuration according to claim 1, including a semiconductor body on which the circuit configuration is integrated.

12. Circuit configuration of an integratable and controllable ring oscillator for generating a clock signal, comprising:

first and second stages being interconnected between supply terminals, an inverter connected between said stages, and a terminal connected between said stages for supplying a clock signal;

each of said stages including first and second transistors having load paths connected between said supply terminals in a series circuit with a connecting point between said transistors, a capacitor connected between said connecting point and a fixed potential, and a decoupling stage connected to said connecting point.