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Non-volatile memory cell with ferroelectric capacitor having logically inactive electrode

  • US 5,038,323 A
  • Filed: 03/06/1990
  • Issued: 08/06/1991
  • Est. Priority Date: 03/06/1990
  • Status: Expired due to Fees
First Claim
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1. In a non-volatile memory array including a source of voltage and a bit line having a parasitic capacitive reactance, a ferroelectric memory cell comprising a capacitor having opposed electrode plates, means connecting the source to one of the electrode plates of the capacitor for applying a constant voltage thereto under two distinct hysteresis states, switching means interconnected between the other of the electrode plates of the capacitor and the bit line for transfer of charge to the bit line during read operations by discharge of the capacitor, means connected to the switching means for isolating the bit line from the capacitor between said read operations, sense means connected to the bit line for detecting changes in voltage level therein during said read operations and means for restoring the capacitor to one of two hysteresis states thereof in response to one of the detected changes in the voltage level.

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