High speed digital packet switching system

• US 5,038,343 A
• Filed: 06/20/1990
• Issued: 08/06/1991
• Est. Priority Date: 06/29/1989
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Vedrenne, Alain, Milewski, Andrzej, Demange, Michel, Lebizay, Gerald
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): KIZOU, HASSAN
• Application Number:
  US07/541,428
• Time in Patent Office: 412 Days
• Field of Search: 370/60, 370/94.1, 370/54, 370/94.3, 370/92
• US Class Current: 370/416
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5651 Priority, marking, classes
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04L 49/1553 Interconnection of ATM switching modules, e.g. ATM switching fabrics
• CPC Class Codes: H04L 49/203 ATM switching fabrics with multicast or broadcast capabilities
• CPC Class Codes: H04L 49/255 Control mechanisms for ATM switching fabrics

Abstract

A 3-stage switching system is provided for generating, i.e. finding, reserving and setting, path from one switch entrance port (1) to at least one switch exit port (transmit side) for asynchronously received and buffered data cells. While an Nth cell is being transferred, control means (36) generate a control word including the switch exit port address for cell (N+1)th to be subsequently transferred. Said control word is used to find and reserve a path through the switch on a stage-by-stage basis, and then set said path, if any, using a fed back acknowledgement. The (N+1)th cell path generation is performed during cell N transfer, on a cycle stealing basis.

Claims

1. A high speed digital packet switching system for transferring asynchronously received data cells, from one multistage switch entrance port to at least one cell destination dependent switch exit port, said system including:

receive buffering means for buffering asynchronously received data cells; and

,

control means for progressively finding and setting the path for the (N+1)th cell to be transferred through said switch, while current Nth cell is being transferred, said control means including;

control word generating means for generating a control word including a cell destination address field and for feeding said field with a destination address for the (N+1)th cell;

cycle stealing means for stealing parts of a cell transfer cycle;

path generating means sensitive to said cycle stealing means and to said control word generating means, for progressively setting up a path during the transfer of said Nth cell, wherein said path is to be used to transfer the (N+1)th cell.

2. A high speed digital packet switching system according to claim 1 wherein said data cells include an information section and a header section, whereby said control word destination address is derived from said cell header section.

3. A high speed digital packet switching system according to claim 1 or 2 wherein said cycle stealing means include:

means for repetitively stealing Nth cell transfer processing cycles;

means sensitive to said cycle stealing occurrence for triggering said (N+1)th path generating means at each cycle stealing occurrence; and

,

first means for neutralizing, within the Nth cell transfer processing, subsequent cycle stealing for cell (N+1)th path setting after finding a path, unless broadcasting (N+1)th cell is being required.

4. A high speed digital packet switching system according to claim 3 wherein said control means include means for inserting an acknowledgement ACK data into said control word upon finding a switch path for said (N+1)th cell transfer, and means for feeding said acknowledgement back to the switch entrance port for said (N+1)th cell, whereby said found path is being set.

5. A high speed digital switching system according to claim 4, wherein said multistage switch is a 3-stage switch, and said control means include:

coding means for differently coding acknowledgement data from stage 2 NACK-2 and from stage 3 NACK-3 upon failing to find free path in stage 2 or 3 respectively;

means for resuming path generating over stages 1 and 2, at next cycle stealing occurrence with same control word, upon said switch entrance port control means getting a NACK-2 back;

or resuming said path generating operations with a different control word upon said control means getting a NACK-3.

6. A system according to claim 5 wherein said means for resuming path generating upon said entrance port control means getting a NACK-3 back, include:

means for scanning the cells enqueued into same receive buffer means and for sequentially comparing the buffered cells destination addresses with last failed (N+1)th cell destination address; and

,

second means, sensitive to said scanning means, for neutralizing subsequent cycle steals during currently processed Nth cell upon said comparing failing to detect a buffered cell with a destination address different from failed (N+1)th cell, otherwise, holding currently investigated (N+1)th cell transfer path finding momentarily and resuming path finding process with a different enqueued cell.

7. A system according to claim 6 wherein said control means include:

means for routing words control words within stage 1 by associating stage 1 entrance and exit ports to each other, according to a predefined scheme; and

,

means for routing the path finding control word within stages 2 and 3 according to the destination address within said control word.

8. A system according to claim 7 wherein said predefined scheme is such that each entrance port is made to route control words through different ones of the exit ports.

9. A system according to claim 8 wherein said means for routing within stages 2 and 3 include means for resolving contention situations by selecting the control word with highest priority bits in its priority field.

10. A system according to claim 5 wherein each of said switch stages includes a plurality of modules, each module including:

a matrix of cross points PCi,j, wherein i=1, . . . M and j=1, . . . M respectively refer to matrix entrance and exit ports;

entrance controller means (CEi) connected to each module entrance port;

exit controller means (CSj) connected to each module exit port;

control means for feeding entrance controller means with said control word defining a stage exit port for data cell (N+1) during transfer of Nth cell, said (N+1)th cell control word being to be transferred to said stage exit port;

control means connected to exit controller means for processing failing path determination if (N+1)th control word defined stage exit port is not free;

acknowledgement means connected to said control means for generating and feeding acknowledgement data back to concerned entrance controller means, whereby said acknowledgement data either acknowledges finding a path through the stage for cell (N+1)th and reserves said path, or said acknowledgement data indicates busy path, whereby the path finding operations should be resumed later on.

11. A system according to claim 7 wherein said means for routing within stage 3 includes means for resolving contention situations by selecting control words in a descending order with a highest priority word being on a first entrance port.

12. A system according to claim 7 wherein said means for routing within stage 2 includes means for resolving contention situations by sequentially selecting each entrance port as the highest priority port.

13. An improved packet switching system comprising:

a switch means having a plurality of crosspoint switches to be set up to provide transmission paths;

a receive buffering means, coupled to the switch means, for receiving and buffering packets to be routed through the transmission paths;

a first control means coupled to the switch means and the receive buffering means, said first control means accessing the switch means for finding and setting up the transmission paths along which the packets are routed; and

a second control means coupled to the first control means;

said second control means stealing parts of packets transfer cycle to set up a transmission path for a next packet in the receive buffering means.