Redundancy control circuit employed with various digital logic systems including shift registers

• US 5,038,368 A
• Filed: 02/02/1990
• Issued: 08/06/1991
• Est. Priority Date: 02/02/1990
• Status: Expired due to Term

• Current Assignee: Iljin Diamond Co.,Ltd. (Iljin Holdings Company Limited)
• Original Assignee: David Sarnoff Research Center, Inc.
• Inventors: Lee, Swye N.
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US07/473,751
• Time in Patent Office: 550 Days
• Field of Search: 307/202.1, 307/219, 307/441, 371/8.1, 371/8.2, 371/9.1, 371/10.1, 365/200, 377/28, 377/68
• US Class Current: 377/28
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G11C 29/86 in serial access memories, e.g. shift registers, CCDs, bubble memories

Abstract

A redundancy circuit that substitutes a redundant circuit element for a corresponding defective circuit element includes a severable fuse link and a redundancy control circuit with an input connected to the severable fuse link and first and second outputs. When the fuse link is intact, the first output of the redundancy control circuit is in a first state and the second output is in a second state. When the fuse link is severed, a momentary signal on power up places the first output in the second state and the second output in the first state. The first output is coupled to the one circuit element and the second output is coupled to the corresponding redundant circuit element. If the one circuit element is defective, it is disabled by severing the fuse link.

Claims

1. A redundancy circuit comprising:

a first circuit element;

a second circuit element; and

a redundancy control circuit for disabling one of the first and second circuit elements comprising;

a severable fuse link having first and second terminals;

means for receiving a momentary signal;

a control circuit having an input and first and second output terminals;

the second terminal of the severable fuse link being coupled to the control circuit input; and

means connected to the second terminal of the severable fuse link responsive to the fuse link being intact for placing the first output terminal of the control circuit in a first state and the second output terminal of the control circuit in a second state and jointly responsive to a momentary signal applied to the receiving means and the fuse link being severed for placing the first output terminal of the control circuit in the second state and the second output terminal of the control circuit in the first state; and

the first output terminal of the control circuit being coupled to the first circuit element and the second output terminal of the control circuit being coupled to the second circuit element.

2. The circuit of claim 1 wherein the control circuit comprises:

first and second inverters each having an input and an output;

the output of the first inverter being coupled to first output terminal of the control circuit;

the output of the second inverter being coupled to second output terminal of the control circuit;

the output of the first inverter being coupled to the input of the second inverter; and

means for coupling the output of the second inverter to the input of the first inverter.

3. The circuit of claim 2 wherein:

the means for placing the first output terminal of the control circuit in the first state and the second output terminal of the control circuit in a second state and for placing the first output terminal of the control circuit in the second state and the second output terminal of the control circuit in the first state comprises;

semiconductor switching means having an output electrode and a control electrode

the output electrode of the semiconductor switching means being connected to the second terminal of the fuse link; and

the control electrode of the semiconductor switching means being coupled to the momentary receiving means.

4. The circuit of claim 3 further comprising:

means for receiving a first voltage;

the first terminal of the severable fuse link being coupled to the first voltage receiving means; and

the output electrode of the semiconductor switching means being placed in a first voltage state responsive to the severable fuse link being intact and being placed in a second voltage state jointly responsive to the momentary signal at the control electrode of the semiconductor switching means and the fuse link being severed.

5. The circuit of claim 4 wherein the means for coupling the output of the second inverter to the input of the first inverter comprises gating means, which is coupled between the output of the second inverter and the input of the first inverter, responsive to the momentary signal for disconnecting the input of the first inverter from the output of the second inverter.

6. The circuit of claim 5 wherein the semiconductor switching means comprises:

a field effect transistor having a drain electrode and a gate electrode;

the output electrode of the semiconductor switching means being the drain electrode of the field effect transistor; and

the control electrode of the switching means being the gate electrode of the field effect transistor.

7. The circuit of claim 6 wherein the field effect transistor is an n-channel field effect transistor.

8. The circuit of claim 7 wherein the n-channel field effect transistor is an n-channel thin film field effect transistor.

9. The circuit of claim 1 wherein:

the first circuit element comprises a first digital register having output gating means;

the second circuit element comprises a second digital register having output gating means;

the first output terminal of the control circuit being coupled to the output gating means of one of the first and second digital registers; and

the second output terminal of the control circuit being coupled to the output gating means of the other of the first and second digital registers.

10. Redundancy control circuitry comprising:

first and second circuit elements;

a severable fuse link;

the redundancy control circuitry having an input terminal for receiving a monetary signal, a first output terminal coupled to the first circuit element, a second output terminal coupled to the second circuit element, and being adapted to disable one of the first and second circuit elements when the fuse link in intact and being adapted to disable the other of the first and second circuit elements when the fuse link is severed;

first and second inverters each having an input and an output;

means coupled to the redundancy control circuit input terminal for selectively coupling the output of the second inverter to the input of the first inverter;

the output of the first inverter being coupled to the input of the second inverter and to the first output terminal of the redundancy control circuitry;

the output of the second inverter being coupled to the second output terminal of the redundancy control circuitry; and

a semiconductor switching means having an output electrode coupled to the fuse link and to the input of the first inverter, and having a control electrode coupled to the input terminal of the redundancy control circuitry.

11. The redundancy control circuitry of claim 10 wherein the semiconductor switching means is a field effect transistor.

12. The redundancy control circuitry of claim 11 wherein the field effect transistor is an n-channel insulated gate field effect transistor.

13. The redundancy control circuitry of claim 10 wherein the means coupled to the redundancy control circuit comprises a transmission gate.

14. The redundancy control circuitry of claim 13 wherein:

the transmission gate comprises a second and third field effect transistor which are complementary with each having a drain, a source and a gate;

the drain of the second transistor is coupled to the source of the third transistor and to the input of the first inverter;

the source of the second transistor is coupled to the drain of the third transistor and to the output of the second inverter; and

the gate of one of the second and third transistors being coupled to the redundancy control circuitry input terminal, and the gate of the other of the second and third transistors being coupled through an inverter to the redundancy control circuitry input terminal.

15. Redundant shift register circuitry comprising:

first and second shift registers with each having at least first and second stages and with each stage having an input and an output;

a first pair of first and second coupling control circuits and a second pair of third and fourth coupling circuits with each of the coupling circuits having an input terminal, an output terminal and a control terminal;

the output of the first stage of the first shift register being coupled to the inputs of the first and second coupling control circuits;

the output of the first stage of the second shift register being coupled to the inputs of the third and fourth coupling control circuits;

the output terminals of the first and third coupling control circuits being coupled to the input of the second stage of the first shift register;

the output terminals of the second and fourth coupling control circuits being coupled to the input of the second stage of the second shift register;

a severable fuse link;

redundancy control circuitry having an input terminal for receiving a monetary signal, a first output terminal coupled to the control terminals of the first and second coupling control circuits, and a second output terminal coupled to the control terminals of the third and fourth coupling control circuits;

the redundancy control circuitry being adapted to disable one of the first and second pairs of coupling control circuits when the fuse link in intact and being adapted to disable the other pair of coupling control circuits when the fuse link is severed;

the redundancy control circuitry comprising;

first and second inverters each having an input and an output;

means coupled to the redundancy control circuit input terminal for selectively coupling the output of the second inverter to the input of the first inverter;

the output of the first inverter being coupled to the input of the second inverter and to the first output terminal of the redundancy control circuitry;

the output of the second inverter being coupled to the second output terminal of the redundancy control circuitry; and

a semiconductor switching means having an output electrode coupled to the fuse link and to the input of the first inverter, and having a control electrode coupled to the input terminal of the redundancy control circuitry.

16. The redundancy control circuitry of claim 15 wherein the semiconductor switching means is a field effect transistor.

17. The redundancy control circuitry of claim 16 wherein the field effect transistor is an n-channel insulated gate field effect transistor.

18. The redundancy control circuitry of claim 16 wherein the means coupled to the redundancy control circuit input terminal comprises a first transmission gate and the first, second, third and fourth coupling control circuits comprise second, third, fourth and fifth transmission gates, respectively.

19. The redundancy control circuitry of claim 18 wherein each of the transmission gates comprises second and third field effect transistor which are complementary with each having a drain, a source and a gate.

20. Redundancy circuitry comprising:

a severable fuse link;

the redundancy circuitry having an input and first and second outputs with the first output being connectable to a first circuit element and the second output being connectable to a second circuit element;

the first and second circuit elements being essentially identical and each being adapted to be enabled by a first logic level and disabled by a second logic level;

a first control circuit having an input coupled to the input of the redundancy circuitry and having an output;

a second control circuit having first and second inputs and first and second outputs;

the first input of the second control circuit being coupled to the redundancy circuitry input terminal;

the second input of the second control circuit being coupled to the severable fuse link and to the output of the first control circuit;

the first and second outputs of the second control circuit being coupled to the first and second redundancy circuitry outputs, respectively;

the first control circuit being adapted upon receipt of a control signal applied to the input thereof to generate at the output thereof a first logic level when the severable fuse link is intact and to generate at the output thereof a second logic level when the severable link fuse is severed; and

the second control circuit being adapted to generate a first set of complementary logic levels at the first and second redundancy circuitry output terminals upon receipt of the first logic level from the first control circuit and to generate a second set of complementary logic levels on the first and second outputs of the redundancy circuitry which are opposite to the first set of complementary logic levels.

21. The redundancy circuitry of claim 20 in which the second control circuit comprises:

first and second inverters each having an input and an output;

the output of the first inverter being coupled to the input of the second inverter and to the first redundancy circuitry output;

the output of the second inverter being coupled to the second redundancy circuitry output;

the input of the first inverter being coupled to the severable fuse link and to the output of the first control circuit;

a transmission gate connected between the output of the second inverter and the input of the first inverter; and

the transmission gate having a control input coupled to the redundancy circuitry input.

22. The redundancy circuitry of claim 21 in which the first control circuit comprises:

a transistor having output and control electrodes;

the transistor output electrode being coupled to the several fuse link; and

the transistor control electrode being coupled to receive a control signal applied to the redundancy circuitry input.