Method of producing a quasi-flat semiconductor device capable of a multi-wavelength laser effect and the corresponding device

• US 5,039,627 A
• Filed: 01/17/1990
• Issued: 08/13/1991
• Est. Priority Date: 01/20/1989
• Status: Expired due to Fees

• Current Assignee: ETAT Francais Ministre Des Postes Telecommunications et de L'Espace
• Original Assignee: ETAT Francais Ministre Des Postes Telecommunications et de L'Espace
• Inventors: Menigaux, Louis, Dugrand, Louis
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Bunch, William D.
• Application Number:
  US07/466,591
• Time in Patent Office: 573 Days
• Field of Search: 148/DIG. 39, 148/56, 148/64, 148/65, 148/72, 148/84, 148/95, 148/131, 148/169, 148/33.4, 148/33.5, 156/643, 156/648, 156/649, 156/652, 156/656, 156/662, 372/48, 372/50, 372/97, 372/46, 372/43, 437/81, 437/51, 437/54, 437/65, 437/126, 437/129, 437/133, 437/105, 437/107, 437/108, 437/110, 437/905, 437/924, 437/987
• US Class Current: 438/35
• CPC Class Codes: H01L 33/0062 for devices with an active region comprising only III-V compounds
• CPC Class Codes: H01S 5/4031 Edge-emitting structures
• CPC Class Codes: H01S 5/4043 with vertically stacked active layers
• CPC Class Codes: H01S 5/4087 emitting more than one wavelength
• CPC Class Codes: Y10S 148/072 Heterojunctions
• CPC Class Codes: Y10S 148/095 Laser devices

Abstract

A method of producing a quasi-flat semiconductor device capable of a multi-wavelength laser effect and the device thus produced.

On the basis of a double heterostructure stack supported by a substrate comprising steps, following levelling of the stack and diffusion through a flat surface, a semiconductor device is obtained which is capable of a multi-wavelength laser effect, of which the different junctions are situated in a plane parallel with the base of the substrate.

Claims

1. A method of producing a semiconductor device, in particular a device capable of a laser effect, comprising the steps of:

a) forming a substrate in stair-step configuration having elongated treads which are parallel with one another and separated from one another by transitions;

b) disposing on said substrate a mono-crystalline double heterostructure stack comprising alternating confinement layers and active layers, wherein said active layers have compositions different from one another, each said confinement and active layer being assigned a numerical rank in order of said disposing on said substrate, all said layers having the same type of conductivity, producing thereby parallel stages parallel with said treads;

c) levelling said stack to obtain a block having a substantially flat free upper surface;

d) forming a substantially flat upper layer on at least a part of said substantially flat free upper surface of said stack;

e) introducing impurities of a conductivity opposite to that of the confinement layers through said substantially flat upper layer which has the same type of conductivity as said impurities or a low but opposite conductivity, into the stack of said block, said impurities forming parallel and elongated strips and producing P-N junctions within the stack which are electrically and individually operable and insulated from one another, the P-N junctions of at least two adjacent strips being formed in the vicinity of active layers of different rank and composition; and

f) optically preparing the small opposite ends of said strips.

2. A method according to claim 1, wherein said comprises erosion by a photo etching process.

3. A method according to claim 1, wherein the double heterostructure comprises group III-V alloys.

4. A method according to claim 3, wherein the double heterostructure comprises at least one material selected from the group consisting of aluminum, gallium and indium and at least one material selected from the group consisting of phosphorous, arsenic and antimony.

5. A method according to claim 4, wherein the active layers are of type N, and comprise Ga_1-x Al_x As, x differing each time, and being less than approximately 10%, while the confining layers comprise Ga_l-y Al_y As, y being substantially the same for all and equal to approximately 30%.

6. A method according to claim 1, wherein the layers of the double heterostructure are deposited by epitaxy.

7. A method according to claim 1, wherein the thickness of the active layers is about one-tenth of a micron while the thickness of the confining layers is on the order of 1 micron.

8. A method according to claim 1, wherein said upper layer deposited by epitaxy.

9. A method according to claim 8, wherein the thickness of the upper layer is about one-tenth of a micron.

10. A method according to claim 1, wherein the upper layer is a group III-V alloy.

11. A method according to claim 5, wherein the upper layer is type P gallium arsenide.

12. A method according to claim 1, wherein said levelling comprises an erosion operation applied to the upper surface of the block, laying bare at least over the major part of the eroded surface of the stack, the upper portion of an active layer which serves as an upper layer.

13. A method according to claim 1, wherein regions of an inverted type are formed by the introduction of impurities, said regions extending from the upper layer as far as the active layer of the desired rank in order respectively to form said P-N junctions.

14. A method according to claim 13, wherein said impurities are selected from the group consisting of zinc, cadmium, magnesium and beryllium.

15. A method according to claim 13, wherein the said regions are localized.

16. A method according to claim 13, wherein said regions form one single continuous zone of an inverted type.

17. A method according to claim 13, wherein said regions are formed by diffusion.

18. A method according to claim 13, wherein said regions are formed by ionic implantation followed by annealing.

19. A method according to claim 13, wherein the P-N junctions are electrically insulated from one another by localized eroding between said inverted type regions by a dry or wet process, in order to engrave or etch grooves extending from said upper layer as far as at least beyond each P-N junction situated on either side of the groove, which makes it possible to accommodate said strips.

20. A method according to claim 13, wherein said P-N junctions are insulated electrically by proton implantation between said inverted type regions in order to accommodate said strips.

21. A method according to claim 13, additionally comprising depositing an individual metallic contact on each inverted type region and a common metallic contact on the substrate.

22. A method according to claim 1, wherein said optically preparing comprises a splitting process.

23. A method according to claim 1, wherein said optically preparing comprises a wet or dry machining stage.

24. A method according to claim 1, wherein the substrate comprises a group III-V alloy which is heavily doped with the same type of conductivity as the layers in the stack, in contact with the bottom confinement layer in the stack.

25. A method according to claim 24, wherein the substrate further comprises a group III-V alloy or silicon.

26. A method according to claim 1, wherein said step of forming the substrate also comprises forming a transverse riser extending in a plane substantially at right-angles to each transition and defining on said substrate lower and upper bottoms for said stack, and wherein said disposing step comprises an additional step to produce within the stack at least in the sector supported by the upper bottoms, a transparent layer forming a light guide for light emissions from the P-N junctions.

27. A method according to claim 6, wherein said layers of the double heterostructure are deposited by liquid phase epitaxy, molecular beam epitaxy, or vapor phase deposition of organometallic compounds.

28. A method of producing a semiconductor device, in particular a device capable of a laser effect, comprising the steps of:

a) forming a substantially flat substrate and disposing thereon a mono-crystalline double heterostructure stack comprising alternate confinement layers and active layers, wherein said active layers have compositions different from one another, each said confinement and active layer being assigned a numerical rank in order of said disposing on said substrate, all said layers having the same type of conductivity, said stack having a substantially flat free upper surface;

b) forming a substantially flat upper layer on at least a part of said substantially flat free upper surface of said stack;

c) introducing impurities of a type of conductivity opposite to that of the confinement layers through said substantially flat upper layer which has the same type of conductivity as said impurities or a low but opposite conductivity, into the stack of said block, said impurities forming parallel and elongated strips and producing P-N junctions within the stack which are electrically and individually operable and insulated from one another, the P-N junctions of at least two adjacent strips being formed in the vicinity of active layers of different rack and composition; and

d) optically preparing the small opposite ends of said strips.

29. A method according to claim 28, wherein the double heterostructure comprises group III-V alloys.

30. A method according to claim 29, wherein the double heterostructure comprises alloys of at least one material selected from the group consisting of aluminum, gallium and indium and at least one material selected from the group consisting of phosphorous, arsenic and antimony.

31. A method according to claim 30, wherein the active layers are of type N, and comprises Ga_1-x Al_x As, x differing each time and being less than approximately 10%, while the confinement layers comprise Ga_1-y Al_y As, y being substantially the same for all and equal to approximately 30%.

32. A method according to claim 28, wherein the layers of the double heterostructure are deposited by epitaxy.

33. A method according to claim 32, wherein the layers of the double heterostructure are deposited by liquid phase epitaxy, molecular beam epitaxy or vapor phase deposition of organometallic compounds.

34. A method according to claim 28, wherein the thickness of the active layers is about one-tenth of a micron while the thickness of the confinement layers is on the order of 1 micron.

35. A method according to claim 28, comprising depositing said upper layer on at least a part of said free upper surface of said stack by epitaxy.

36. A method according to claim 35, wherein the thickness of the upper layer is about one-tenth of a micron.

37. A method according to claim 28, wherein the upper layer is group III-V alloy.

38. A method according to claim 31, wherein the upper layer is a type P gallium arsenide.

39. A method according to claim 28, comprising formation of regions of an inverted type by the introduction of said impurities, said regions extending from the upper layer as far as the active layer of the desired rank in order respectively to form said P-N junctions.

40. A method according to claim 39, wherein said regions are formed by impurities selected from the group consisting of zinc, cadmium, magnesium and beryllium.

41. A method according to claim 39, wherein said regions are localized.

42. A method according to claim 39, wherein said regions form one single continuous zone of an inverted type.

43. A method according to claim 39, wherein said regions are formed by diffusion.

44. A method according to claim 39, wherein said regions are formed by ionic implantation followed by annealing.

45. A method according to claim 39, wherein the P-N junctions are electrically insulated from one another by localized eroding between said inverted type regions by a dry or wet process, in order to engrave or etch grooves extending from the said upper layer as far as at least beyond each P-N junction situated on either side of the groove, which makes it possible to accommodate said strips.

46. A method according to claim 39, wherein said P-N junctions are insulated electrically by proton implantation between said inverted type regions in order to accommodate said strips.

47. A method according to claim 39, comprising depositing an individual metallic contact on each inverted type region and a common metallic contact on the substrate.

48. A method according to claim 28, wherein said optically preparing comprises a splitting process.

49. A method according to claim 28, wherein said optically preparing comprises a wet or dry machining stage.

50. A method according to claim 28, wherein the substrate comprises a group III-V alloy which is heavily doped with the same type of conductivity as the layers in the stack, in contact with the bottom confinement layer in the stack.

51. A method according to claim 50, wherein the substrate further comprises a group III-V alloy or silicon.

52. A method according to claim 28, additionally comprising eroding said free upper surface of the stack to lay bare at least over a major part of the eroded surface, an upper portion of an active layer which serves as said upper layer.