MOS type field effect transistor formed on a semiconductor layer on an insulator substrate

• US 5,040,037 A
• Filed: 12/11/1989
• Issued: 08/13/1991
• Est. Priority Date: 12/13/1988
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yamaguchi, Yasuo, Kusunoki, Shigeru
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): DANG, HUNG XUAN
• Application Number:
  US07/448,119
• Time in Patent Office: 610 Days
• Field of Search: 357/23.7, 357/23.4, 357/67 S
• US Class Current: 257/347
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical

Abstract

A SOI-MOSFET formed on a thin semiconductor layer (3) having a thickness not more than 1500Å includes a charge carrier absorbing region (9a, 9b, 9c) contacting with at least a portion of the bottom of a channel region (6) of a first conductivity type and with at least a portion of the bottom of a source region (7, 7a) of a second conductivity type. The carrier absorbing region (9a, 9b, 9c) absorbs excess carriers of the first conductivity type contained in the channel region (6).

Claims

1. A SOI-MOSFET comprising:

source and drain regions formed of respective impurity regions of a first type in a thin semiconductor layer deposited not more than 1500 Å

in thickness on an insulator;

a channel region of a second impurity type formed in said thin semiconductor layer between said source region and said drain region, said channel region having a predetermined impurity concentration;

a gate electrode positioned adjacent said channel region and separated from said semiconductor layer by an insulator layer deposited on said semiconductor layer;

at least one floating carrier storage region having an impurity concentration of the second type higher than the predetermined impurity concentration of said channel region for removing and storing excess carriers of the second type from said channel region into said at least one floating carrier storage region, and

an insulating film formed on upper surfaces of said source and drain regions and in lateral contact with, and completely covering, side edges of said source drain regions and of said at least one floating carrier storage region.

2. A SOI-MOSFET according to claim 1, wherein said at least one carrier storage region is formed in said semiconductor layer in contact with a portion of the bottom of said channel region and with a portion of the bottom of said source region.

3. A SOI-MOSFET according to claim 2, further comprising a second carrier storage region formed in said semiconductor layer in contact with a portion of the bottom of said channel region and with a portion of the bottom of said drain region.

4. A SOI-MOSFET comprising:

source and drain regions formed of respective impurity regions of a first type in a thin semiconductor layer deposited not more than 1500 Å

in thickness on an insulator;

a channel region of a second impurity type formed in said thin semiconductor layer between said source region and said drain region, said channel region having a predetermined impurity concentration;

a gate electrode positioned adjacent said channel region and separated from said semiconductor layer by an insulator layer deposited on said semiconductor layer;

a carrier storage region having an impurity concentration of the second type higher than the predetermined impurity concentration of said channel region whereby excess carriers of the second type are removed from said channel region into said carrier storage region;

said carrier storage region being formed in said semiconductor layer in contact with at least a portion of the bottom of said channel region and with at least a portion of the bottom of said source region; and

a metal silicide layer formed on said source region and having a non-uniform depth, a portion of said metal silicide layer being of such depth that said portion of said metal silicide layer is passed locally through said source region to reach said carrier storage region.

5. A SOI-MOSFET comprising:

source and drain regions formed of respective impurity regions of a first type in a thin semiconductor layer deposited not more than 1500 Å

in thickness on an insulator;

a channel region of a second impurity formed in said thin semiconductor layer between said source region and said drain region, said channel region having a predetermined impurity concentration;

a gate electrode positioned adjacent said channel region and separated from said semiconductor layer by an insulator layer deposited on said semiconductor layer;

a carrier storage region having an impurity concentration of the second type higher than the predetermined impurity concentration of said channel region whereby excess carriers of the second type are removed from said channel region into said carrier storage, said carrier storage region being formed in said semiconductor layer in contact with at least a portion of the bottom of said channel region and with at least a portion of the bottom of said source region; and

an aluminum layer formed on said source region, said aluminum layer including alloy spikes locally passing through said source region to reach said carrier storage region.

6. A SOI-MOSFET comprising:

source and drain regions formed of respective impurity regions of a first type in a thin semiconductor layer deposited not more than 1500 Å

in thickness on an insulator, said drain region including a lightly doped drain;

a channel region of a second impurity type formed in said thin semiconductor layer between said source region and said drain region, said channel region having a predetermined impurity concentration;

a gate electrode positioned adjacent said channel region and separated from said semiconductor layer by an insulator layer deposited on said semiconductor layer; and

at least one carrier storage region having an impurity concentration of the second type higher than the predetermined impurity concentration of said channel region whereby excess carriers of the second type are removed from said channel region into said carrier storage region.

7. A SOI-MOSFET according to claim 6, wherein said source region includes a lightly doped source.

8. A SOI-MOSFET according to claim 7, wherein said storage region is formed beneath said lightly doped source.

9. A SOI-MOSFET according to claim 8, further comprising a second carrier storage region formed beneath said lightly doped drain.

10. A SOI-MOSFET comprising:

source and drain regions formed of respective impurity regions of a first type in a thin semiconductor layer deposited not more than 1500 Å

in thickness on an insulator,

a channel region of a second impurity type formed in said thin semiconductor layer between said source region and said drain region;

a gate electrode positioned adjacent said channel region and separated from said semiconductor layer by an insulator layer deposited on said semiconductor layer; and

a crystal defect region having crystal defects whereby excess carriers of the second type are removed from said channel region into said crystal defect region.

11. A SOI-MOSFET according to claim 10, wherein said crystal defect region is formed in at least said channel region at a lower layer portion in the vicinity of said source region.

12. A SOI-MOSFET according to claim 11, wherein said crystal defect region extends into a lower layer portion of said source region.

13. A SOI-MOSFET comprising in combination,

an insulator;

a thin semiconductor layer deposited on said insulator;

a source region and a drain region formed of respective impurity regions of a first type in said thin semiconductor layer;

a channel region of a second impurity type formed in said thin semiconductor layer between said source region and said drain region;

a gate electrode positioned adjacent said channel region and separated from said thin semiconductor layer by an insulator layer deposited on said thin semiconductor layer;

at least one floating carrier removal means for removing and storing excess carriers of the second type from said channel region into said at least one carrier removal means, and

an insulating film formed on upper surfaces of said source and drain regions, and in lateral contact with, and completely covering, side edges of source and drain regions and of said at least one floating carrier storage region;

wherein

said thin semiconductor layer is not more than 1500 Å

thick such that application of a voltage to said gate electrode will cause the channel region as a whole to form a depletion layer.

14. A SOI-MOSFET according to claim 13, wherein:

said channel region has a predetermined concentration of the second type impurities, and

said at least one carrier removal means comprises a carrier storage region having an impurity concentration of the second type higher than the predetermined impurity concentration of said channel region whereby the excess carriers of the second type are removed from said channel region into said carrier storage region.

15. A SOI-MOSFET according to claim 14, wherein said drain region comprises a lightly doped drain.

16. A SOI-MOSFET according to claim 15, wherein said source region comprises a lightly doped source.

17. A SOI-MOSFET according to claim 14, wherein:

the predetermined impurity concentration in said channel region is in the range of 10¹⁶ to 10¹⁷ atoms/cm³ ; and

the predetermined impurity concentration in said carrier storage region is in the range of 10¹⁷ to 10¹⁹ atoms/cm³.

18. A SOI-MOSFET according to claim 13, wherein said at least one carrier removal means comprises a crystal defect region having crystal defects whereby the excess carriers of the second type are removed from said channel region into said crystal defect region.

19. A SOI-MOSFET according to claim 14, wherein said source region comprises:

a source having a first predetermined concentration of second type impurities; and

a lightly doped source having a second predetermined concentration of second type impurities, wherein said second predetermined concentration is lower than said first predetermined concentration.

20. A SOI-MOSFET according to claim 14, wherein said drain region comprises:

a drain having a first predetermined concentration of second type impurities; and

a lightly doped drain having a second predetermined concentration of second type impurities, wherein said second predetermined concentration is lower than said first predetermined concentration.

21. A SOI-MOSFET according to claim 20, wherein said first predetermined concentration of second type impurities is in the range of 10¹⁹ to 10²¹ atoms/cm³ ;

and said second predetermined concentration of second type impurities is in the range of 10¹⁷ to 10¹⁸ atoms/cm³.

22. A SOI-MOSFET according to claim 19, wherein said first predetermined concentration of second type impurities is in the range of 10¹⁹ to 10²¹ atoms/cm³ ;

and said second predetermined concentration of second type impurities is in the range of 10¹⁷ to 10¹⁸ atoms/cm³.