Information processing system having microprogram-controlled type arithmetic processing unit with clock synchronization instruction

• US 5,040,108 A
• Filed: 04/23/1990
• Issued: 08/13/1991
• Est. Priority Date: 04/07/1987
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kanazawa, Takashi
• Primary Examiner(s): Anderson, Lawrence E.
• Application Number:
  US07/513,228
• Time in Patent Office: 477 Days
• Field of Search: 364/200 MS File, 364/ 900 MS File
• US Class Current: 713/375
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G06F 11/1679 at clock signal level
• CPC Class Codes: G06F 11/2028 eliminating a faulty processor or activating a spare
• CPC Class Codes: G06F 11/2048 where the redundant components share neither address space nor persistent storage

Abstract

A method of exchanging information in a processing system including the steps of issuing a clock synchronizing instruction from an operating system, holding the clock synchronizing instruction in a communication information holding unit, suppressing the updating of internal state information in a first arithmetic unit in response to the holding signal, outputting a communication demand signal from the communication information holding unit to a system control unit, freezing the updating of the calendar clock values in respective first and second arithmetic processing units, receiving in the system control unit the first clock value from the first arithmetic processing unit, storing the first calendar clock value in the second arithmetic processing unit, issuing a restarting signal to the arithmetic processing units, and issuing a microprogram actuating instruction to the arithmetic processing units from the system control unit.

Claims

1. A method of exchanging information in an information processing system comprising the steps of:

a) issuing a clock synchronizing instruction from an operating system;

b) holding said clock synchronizing instruction in a communication information holding means;

c) suppressing the updating of internal state information in a first arithmetic processing unit in response to a holding signal from said communication information holding means;

d) outputting a communication demand signal from said communication information holding means to a system control unit;

e) freezing the updating of a first calendar clock value in said first arithmetic processing unit, and freezing the updating of a second calendar clock value in a second arithmetic processing unit;

f) receiving in said system control unit said first calendar clock value from said first arithmetic processing unit;

g) storing in said second arithmetic processing unit said first calendar clock value;

h) issuing a restarting signal from said system control unit to said first and second arithmetic processing units, said restarting signal defreezing the updating of the first and second calendar clock values; and

i) issuing a microprogram actuating instruction from said system control unit to said first arithmetic processing unit and to said second arithmetic processing unit.