Neural network employing leveled summing scheme with blocked array

• US 5,040,134 A
• Filed: 05/26/1989
• Issued: 08/13/1991
• Est. Priority Date: 05/26/1989
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Park, Chin S.
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US07/357,411
• Time in Patent Office: 809 Days
• Field of Search: 364/807, 364/819, 364/820, 364/602, 364/604, 364/513, 365/49, 365/185, 307/201, 382/14, 382/15, 382/30, 382/33, 382/35
• US Class Current: 706/34
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G06V 30/194 References adjustable by an adaptive method, e.g. learning
• CPC Class Codes: G11C 15/046 using non-volatile storage elements

Abstract

A novel associative network architecture is described in which a neural network is subdivided into a plurality of smaller blocks. Each block comprises an array of pattern matching cells which is used for calculating the relative match, or Hamming distance, between an input pattern and a stored weight pattern. The cells are arranged in columns along one or more local summing lines. The total current flowing along the local summing lines for a given block corresponds to the match for that block. Each of the blocks are coupled together using a plurality of global summing lines. The global summing lines sum the individual current contributions from the local summing lines of each associated block. Coupling between the local column lines and the global summing lines is achieved by using a specialized coupling device which permits control of the coupling ratio between the lines. By selectively turning on or off various blocks a measure of the match for individual blocks or for groups of blocks representing a subset of the network, may be calculated. Control over the coupling ratio within the blocks also prevents destructive levels of current from building up on the global summing lines.

Claims

1. An associative network comprising a plurality of blocks, each block comprising a plurality of cells arranged so as to form an array for computing the match between two binary patterns, one of said binary patterns being stored within said cells and the other of said binary patterns being applied as an input to said cells, said cells contributing current to a plurality of local summing lines within each said block, said local summing lines summing the individual current contributions from said cells such that the total local current of each block corresponds to said match;

said network further comprising a plurality of global summing lines and wherein each said block further comprises a plurality of coupling devices, each of said coupling devices comprising first and second field-effect devices coupled so as to form a current mirror wherein the current flow through said first field-effect device is a dependent function of the current flow in said second field-effect device, one coupling device being associated with each of said local summing lines for selectively coupling said local summing lines to a global summing line such that said total local current contributes to the total global current flowing in said global summing lines, said total global current corresponding to the total match between said binary patterns for all of said blocks selected within said network; and

means for weighting the coupling strength between said local summing lines within a single block and their associated global summing line independent of all other of said blocks,

said weighting means comprising a third field-effect device coupled in series between said second field-effect device and one of said local summing lines, said third field-effect device having a reference potential coupled to its gate such that when said reference potential is applied to each of said coupling devices within said block said block is activated for purposes of computing said match.

2. The network of claim 1, wherein said coupling device further comprises a fourth field-effect device coupled in series between said first field-effect device and said one of said global summing lines, said fourth field-effect device coupling said current mirror to said global summing lines, the gate of said fourth field-effect device being coupled to said weighting means to control said coupling strength.

3. The network of claim 2 further comprising a fifth field-effect device coupled to said programming means for electrically coupling said global summing lines to said local summing lines to facilitate programming of said cells.

4. The network of claim 3, wherein said first and second field-effect devices are p-channel devices.

5. The network of claim 4, wherein said third, fourth and fifth field-effect devices are n-channel devices.

6. As associative network for computing the Hamming distance between two binary patterns, said network comprising a plurality of blocks and a plurality of global column lines, each of said blocks comprising a plurality of semiconductor cells arranged so as to form an array, said array having a plurality of local column lines, each column line being coupled to a separate column of said cells, each cell of said array producing an output current whose value depends on the relative match between a corresponding element of an input voltage vector and a weight pattern stored in said cell, said output current contributing to the local summing current flowing on each of said local column lines, each of said blocks including a means for selectively coupling each of said local column lines to an associated one of said global column lines on a weighted basis such that the connection strength between said local summing lines and said one of said global summing lines may be dynamically altered on a block-by-block basis with each local summing current selectively contributing to a global summing current whose value corresponds to said Hamming distance.

7. The associative network of claim 6, wherein said cells comprise a plurality of floating gate devices each having a floating gate for collectively storing said weight pattern.

8. The associative network of claim 7, wherein said coupling means comprises a plurality of coupling devices, each of which comprises a current mirror having a first line coupled to said one of said global column lines and a second line coupled to an associated one of said local column lines such that current flow through said local column lines may selectively contribute to the current flowing in said global column lines.

9. The associative network of claim 7, wherein each of said coupling devices comprises first and second field-effect transistors each having their gates coupled together, said first transistor being coupled to one of said global column lines and said second transistor being coupled to said associated one of said local column lines and to its gate so as to form a current mirror wherein the current flow through said first transistor is a dependent function of the current flow in said second transistor.

10. The associative network according to claim 9 or 8, wherein said coupling means permits selectively computing said match within a single block of said network while ignoring all other blocks.

11. The associative network according to claim 10, wherein each of said coupling devices comprises a third field-effect transistor coupled in series between said second transistor and one of said local column lines, said control means further comprising a reference potential coupled to the gate of said third transistor such that when said reference potential is applied to each of said coupling devices within said block, said block is activated for purposes of computing said match.

12. The associative network of claim 11, wherein each of said coupling devices further comprises a fourth field-effect transistor coupled in series between said first field-effect transistor and said one of said global column lines, said fourth field-effect transistor coupling said current mirror to one of said global column lines, the gate of said fourth transistor being coupled to said control means.

13. The associative network of claim 12, wherein said first and said second transistors are p-channel devices.

14. The associative network of claim 13, wherein said third and fourth field-effect transistors are n-channel devices.