Microprocessor controlled rate-responsive pacemaker having automatic rate response threshold adjustment
First Claim
1. In a pacemaker comprising an implantable housing;
- a battery within said housing;
a pacemaker chip within said housing and connected to said battery;
a connector block attached to said housing and said pacemaker chip to which a pacemaker lead may be detachably connected, the improvement comprising;
a microprocessor chip within said housing and connected to said pacemaker chip and said battery;
memory means coupled to said microprocessor chip for storing program data which controls the operation of said microprocessor chip;
sensor means for sensing a physiological parameter and for generating a raw sensor signal as a function thereof;
sensor circuit means for generating one of a plurality of sensor level signals as a function of the average amplitude of said raw sensor signal, and for presenting said sensor level signal to said microprocessor chip;
processing means included in said microprocessor chip, said processing means responsive to the program data stored in said memory means for generating a pacing rate signal which varies in a prescribed manner as a function of the sensor level signal, said pacing rate signal being presented to said pacemaker chip; and
means, included in said pacemaker chip, for responding to said pacing rate signal in order to alter the rate at which pacing pulses are generated by said pacemaker.
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Accused Products
Abstract
A rate-responsive pacemaker which includes a conventional programmable pulse generator, a physiological sensor, and a processor is disclosed which generates heart stimulation pulses on demand, or as otherwise programmed, as controlled by a rate control signal which is derived from the physiological sensor. The physiological sensor generates a raw signal which varies as a function of some physiological parameter, such as activity level to provide some indication of whether the heart rate should increase or decrease, and hence whether the pacemaker should change the rate at which pacing pulses are provided. The processor converts the raw signal to the sensor-indicated rate signal in accordance with a selectable transfer relationship which defines the sensor-indicated rate signal as a function of a set of discrete sensor level index signals. The sensor-indicated rate signal remains at a minimum value or base rate for all sensor level index signals below a prescribed rate response threshold, with this rate response threshold being set automatically by the processor as a function of a running average of the sensor level index signals monitored over a prescribed time period.
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Citations
27 Claims
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1. In a pacemaker comprising an implantable housing;
- a battery within said housing;
a pacemaker chip within said housing and connected to said battery;
a connector block attached to said housing and said pacemaker chip to which a pacemaker lead may be detachably connected, the improvement comprising;a microprocessor chip within said housing and connected to said pacemaker chip and said battery; memory means coupled to said microprocessor chip for storing program data which controls the operation of said microprocessor chip; sensor means for sensing a physiological parameter and for generating a raw sensor signal as a function thereof; sensor circuit means for generating one of a plurality of sensor level signals as a function of the average amplitude of said raw sensor signal, and for presenting said sensor level signal to said microprocessor chip; processing means included in said microprocessor chip, said processing means responsive to the program data stored in said memory means for generating a pacing rate signal which varies in a prescribed manner as a function of the sensor level signal, said pacing rate signal being presented to said pacemaker chip; and means, included in said pacemaker chip, for responding to said pacing rate signal in order to alter the rate at which pacing pulses are generated by said pacemaker. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
- a battery within said housing;
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10. A rate-responsive pacemaker comprising:
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a pulse generator having means for generating pulses at a prescribed rate; state logic means for controlling said pulse generator, including whether a pulse is to be generated and, if so, at what rate, said state logic means comprising; state logic registers which, in combination, assume one of a possible plurality of states as a function of signals applied thereto; memory circuitry addressed by said state logic registers, said memory circuitry having prescribed control signals stored therein at each location which is addressable by said state logic; timing circuitry which generates timing signals; sensing circuitry which generates event signals at the occurrence of prescribed events; and logic circuitry responsive to said control signals, timing signals and event signals having output signals which steer said state logic registers as a function of said control, timing and event signals, said state logic registers continuously cycling through various states as a function of the control, timing and event signals applied to said logic circuitry, a pacing cycle comprising a cycle of said state logic from a prescribed reference state, to at least one other state, and back to said reference state; a physiological sensor which generates a raw sensor signal having an average amplitude that varies as a function of a physiological environment to which said physiological sensor is subjected; a conversion circuit coupled to said sensor, said conversion circuit including means for monitoring the average amplitude of said raw sensor signal and means for generating a discrete sensor level index signal as a function of said average amplitude at least once each pacing cycle, said sensor level index signal thereby assuming one of a plurality of possible sensor level signal values once each pacing cycle; processor means coupled to said conversion circuit for defining a sensor-indicated rate signal as a function of the sensor level index signal for each pacing cycle; and interface means positioned between said processor means and the memory circuitry of said state logic means for selectively injecting said sensor-indicated rate signal into the control signals of said memory circuitry that is presented to said logic circuitry, whereby said sensor-indicated rate signal, when so injected, cooperates with the event and timing signals already present to influence the rate at which pulses are generated by said pulse generator. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A rate-responsive pacing system comprising:
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implantable pulse generator means generating a pacing pulse at a rate set by a rate control signal; means for generating a base rate signal; implantable sensor means for generating a raw sensor signal indicative of a need to change the rate at which said pacing pulses generated by said pulse generator means; implantable processor means coupled to said pulse generator means and said sensor means for generating a sensor-indicated rate signal, said processor means for converting said raw sensor signal into one of a plurality of sensor level index signals at prescribed sample times, said conversion causing one of said plurality of sensor level index signals to be generated as a function of the magnitude of said raw sensor signal at each of the sample times, and further wherein said processor means includes means for defining said sensor-indicated rate signal to assume a value which varies as a function of the average amplitude of the sensor level index signals for a plurality of the sample times; selection means for programmably selecting one of said base rate signal or said sensor-indicated rate signal as the rate control signal controlling said pulse generator means; and automatic reversion means coupled to said selection means for automatically causing said selection means to select one of said base rate signal or said sensor-indicated rate signal as the rate control signal in the event the other of said base rate signal or said sensor-indicated rate signal is not generated. - View Dependent Claims (23, 24, 25, 26, 27)
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Specification