Method of encapsulating an integrated circuit using a punched metal grid attached to a perforated dielectric strip

• US 5,041,395 A
• Filed: 04/05/1990
• Issued: 08/20/1991
• Est. Priority Date: 04/07/1989
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Steffen, Francis
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Graybill, David E.
• Application Number:
  US07/504,961
• Time in Patent Office: 502 Days
• Field of Search: 437/206, 437/207, 437/211, 437/217, 437/219, 437/220, 437/224, 437/8, 437/209, 439/841, 439/827, 439/837, 439/840, 439/68, 206/330, 264/272.17, 357/70, 357/80, 361/398, 361/401, 361/403, 361/404, 361/388, 361/406, 361/408, 361/421, 428/571, 428/572, 228/180.2
• US Class Current: 29/827
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48245 the item being metallic
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/49855 for flat-cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01028 Nickel [Ni]
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: Y10T 29/49121 : Beam lead frame or beam lead device

Abstract

The disclosure concerns the encapsulation of integrated circuit chips, notably with a view to their being incorporated in a chip card. The encapsulation method comprises the formation of a pre-punched metallic conductive grid, the formation of a strip of pre-perforated plastic material, the transfer of a strip to the grid, the positioning of an integrated circuit chip in a perforation of the strip, and the formation of electrical connections between the chip and zones of the grid located in perforations of the strip. The perforations of the strip and the punched slots of the grid are arranged so that the strip covers and blocks all the interstices between conductors of the grid in the useful region corresponding to a module to be made. When a protecting resin is laid, it is confined and does not leak through the interstices of the grid. A plastic or metal ring defines the heightwise dimension of the micromodule.

Claims

1. A method for the encapsulation of an integrated circuit, comprising formation of a prepunched metal conductive grid, formation of a strip of preperforated dielectric screen, transfer of the strip to the grid, positioning of an integrated circuit chip in a perforation of the strip, and formation of electrical connections between the chip and zones of the grid located in perforations of the strip.

3. A method according to claim 1, comprising a step for setting up of protection by a protecting material covering the chip and the connections in the perforations of the strip.

4. A method according to claim 3, comprising a step for positioning, on the strip, of a protecting ring surrounding the chip and its connections, this ring being filled with protecting insulator material after it has been positioned.

5. A method according to claim 3, wherein, the strip has a ring-shaped protuberance surrounding the space reserved for the chip and its connections, and wherein this ring is filled with a protecting material after the chip and its connections have been positioned.

8. A method according to claim 1 or claim 2, wherein the strip is transferred to the screen by bonding or hot transfer.

2. A method for the encapsulation of an integrated circuit, comprising formation of a prepunched metal conductive grid, formation of a strip of preperforated dielectric screen, transfer of the strip to the grid, positioning of an integrated circuit chip in a perforation of the strip, and formation of electrical connections between the chip and zones of the grid located in perforations of the strip, and wherein the perforations of the strip and punched slots of the grid are such that the strip covers and blocks all interstices between conductors of the grid in a region in which a chip may be placed.

9. A method according to claim 2, comprising a step for setting up of protections by a protecting material covering the chip and the connections in the perforations of the strip.

10. A method according to claim 9, comprising a step for positioning, on the strip of a protecting ring surrounding the chip and its connections, this ring being filled with protecting insulator material after it has been positioned.

11. A method according to claim 11, wherein, the strip has a ring-shaped protuberance surrounding the space reserved for the chip and its connections, and wherein this ring is filled with a protecting material after the chip and its connections have been positioned.

6. A method according to any of the claims 3 to 5 or 11 to 13 wherein the protecting material is a thermoplastic or thermosetting resin.

7. A method according to claim 6, wherein the protecting material is an imperfect dielectric to enable the outflow of electrostatic charges.