Parallel clocked latch

• US 5,041,740 A
• Filed: 04/30/1990
• Issued: 08/20/1991
• Est. Priority Date: 04/30/1990
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Smith, Robert T.
• Primary Examiner(s): Hudspeth, David
• Assistant Examiner(s): Sanders, Andrew
• Application Number:
  US07/516,636
• Time in Patent Office: 477 Days
• Field of Search: 307/279, 307/272.1, 307/272.2, 307/481, 307/455
• US Class Current: 327/212
• CPC Class Codes: H03K 3/356043 with synchronous operation

Abstract

A parallel clocked latch circuit having a plurality of inputs and first and second outputs includes a gate circuit responsive to the plurality of inputs for providing first and second logic output signals which are coupled to the first and second outputs of the parallel clocked latch circuit, respectively. A regeneration circuit responsive to the first and second logic output signals for storing logic levels at the first and second outputs of the latch circuit. A level shifting circuit coupled to the gate circuit for providing a predetermined voltage level shift of the logic levels of the gate circuit. A field-effect transistor having a drain coupled to the regeneration circuit, a gate coupled to a control signal, and a source coupled to a lowest level of the gate circuit, the control signal having a first logic state voltage level greater than the voltage level of a first logic state of the gate circuit by a predetermined voltage such that when the control signal is in a first logic state the regeneration circuit is rendered operative and the gate circuit is rendered non-operative. Also, a current source coupled between the source of the field-effect transistor and a first supply voltage terminal.

Claims

1. A parallel clocked latch circuit having a plurality of inputs and first and second outputs, comprising:

an input gate circuit responsive to logic input signals supplied to the plurality of inputs for providing corresponding complementary output logic signals at the first and second outputs when said input gate circuit is rendered operative;

regeneration circuit means coupled to both said input gate circuit and the first and second outputs for maintaining said complementary output logic signals at the first and second outputs when redered operative while said input gate circuit is rendered non-operative;

control circuit means responsive to a clock signal for alternately rendering said input gate circuit and said regenerating circuit means operative and non-operative, said clock signal having a first logic state level that exceeds a first logic state level of said logic input signals of said input gate circuit by a predetermined magnitude such that said clock signal being in a first logic state renders said regeneration circuit means operative and said input gate circuit non-operative; and

level shifting means coupled to said input gate circuit for level shifting said complementary output logic signals.

2. The parallel clocked latch circuit according to claim 1 wherein said control circuit means includes:

a transistor having first, second and control electrodes, said control electrode being coupled to receive said clock signal, said first electrode being coupled to said regeneration circuit means, and said second electrode being coupled to said input gate circuit.

3. The parallel clocked latch circuit according to claim 2 wherein said level shifting means includes:

a resistor coupled between a first supply voltage terminal and said input gate circuit.

4. The parallel clocked latch circuit according to claim 3 wherein said input gate circuit includes:

a first transistor having first, second and control electrodes, said first electrode being coupled to said level shifting means and to the second output, and said control electrode being coupled to a first one of the plurality of inputs;

a second transistor having first, second and control electrodes, said first electrode being coupled to said level shifting means and to the first output, said second electrode being coupled to said second electrode of said first transistor of said input gate circuit, and said control electrode being coupled to a second one of the plurality of inputs;

a third transistor having first, second and contrl electrodes, said first electrode being coupled to said second electrodes of said first and second transistors of said input gate circuit, and said control electrode being coupled to a third one of the plurality of inputs;

a fourth transistor having first, second and control electrode, said first electrode being coupled to said first electrode of said second transistor of said input gate circuit, said second electrode being coupled to said second electrode of said third transistor and to said second electrode of said transistor of said control circuit means, and said control electrode being coupled to a fourth one of the plurality of inputs;

a first resistor coupled between said first electrode of said first transistor and said level shifting means; and

a second resistor coupled between said first electrode of said second transistor and said level shifting means.

5. The parallel clocked latch circuit according to claim 4 wherein said regeneration circuit means includes:

a first transistor having first, second and control electrodes, said first electrode being coupled to the first output, and said control electrode being coupled to the second output; and

a second transistor having first, second and control electrodes, said first electrode being coupled to the second output, said second electrode being coupled to said second electrode of said first transistor of said regeneration circuit means and to said first electrode of said transistor of said control circuit means, and said control electrode being coupled to the first output.

6. A parallel clocked latch circuit having first and second outputs, comprising:

a first field-effect transistor having first, second and control electrodes, said first electrode being coupled to the second and control electrodes, said first electrode being coupled to the second output and to a first supply voltage terminal, and said control electrode being coupled to a first input;

a second field-effect transistor having first, second and control electrodes, said first electrode being coupled to the first output and to said first supply voltage terminal, said second electrode being coupled to said second electrode of said first field-effect transistor, and said control electrode being coupled to a second input,;

a third field-effect transistor having first, second and control electrodes, said first electrode being coupled to said second electrodes of said first and second field-effect transistors, and said control electrode being coupled to a third input;

a fourth field-effect transistor having first, second and control electrodes, said first electrode being coupled to said first electrode of said second field-effect transistor, said second electrode being coupled to said second electrode of said third field-effect transistor, and said control electrode being coupled to a fourth input;

a fifth field-effect transistor having first, second and control electrodes, said control electrode being coupled to a fifth input, and said second electrode being coupled to said second electrodes of said third and fourth field-effect transistors;

a sixth field-effect transistor having first, second and control electrodes, said first electrode being coupled to the first output, and said control electrode being coupled to the second output;

a seventh field-effect transistor having first, second and control electrodes, said first electrode being coupled to the second output, said second electrode being coupled to said second electrode of said sixth field-effect transistor and to said first electrode of said fifth field-effect transistor, and said control electrode being coupled to the first output;

a current source coupled between said second electrodes of said third, fourth and fifth field-effect transistors and a second supply voltage terminal;

a series combination of first and second resistors coupled between said first electrode of said first field-effect transistor and said first supply voltage terminal wherein said second resistor has a first terminal coupled to said first supply voltage terminal; and

a series combination of a third and said second resistors coupled between said first electrode of said second field-effect transistor and said first supply voltage terminal.

7. A parallel clocked latch circuit having first and second outputs, comprising:

gate means responsive to a plurality of input signals for providing logic levels at first and second outputs, said first and second outputs of said gate means being respectively coupled to the first and second outputs of the latch circuit;

level shifting means for providing a predetermined level shift of said logic levels of said gate means;

a first field-effect transistor having a drain coupled to the first output of the latch circuit, a gate coupled to the second output of the latch circuit, and a source;

a second field-effect transistor having a drain coupled to the second output of the latch circuit, a gate coupled to the first output of the latch circuit, and a source coupled to said source of said first field-effect transistor;

a third field-effect transistor having a drain coupled to said sources of said first and second field-effect transistors, a gate coupled to receive a control signal, and a source coupled to said gate means, said control signal having a first logic state level that exceeds a first logic state of said plurality of input signals of said gate means by a predetermined magnitude such that said control signal being in a first logic state renders said first and second field-effect transistors operative and said gate means non-operative; and

a current source coupled between said source of said third field-effect transistor and a first supply voltage terminal.

8. The parallel clocked latch circuit according to claim 7 wherein said gate means includes:

a first field-effect transistor having a drain coupled to said level shifting means and to said second output of said gate means, a gate coupled to a first one of the plurality of inputs, and a source;

a second field-effect transistor having a drain coupled to said level shifting means and to said first output of said gate means, a gate coupled to a second one of the plurality of inputs, and a source coupled to said source of said first field-effect transistor of said gate means;

a third field-effect transistor having a drain coupled to said sources of said first and second field-effect transistors of said gate means, a gate coupled to a third one of the plurality of inputs, and a source;

a fourth field-effect transistor having a drain coupled to said drain of said second field-effect transistor of said gate means, a gate coupled to a fourth one of the plurality of inputs, and a source coupled to said source of said third field-effect transistor of said gate means and to said source of said third field-effect transistor of the latch circuit;

a first resistor coupled between said drain of said first field-effect transistor of said gate means and said level shifting means; and

a second resistor coupled between said drain of said second field-effect transistor of said gate means and said level shifting means.

9. The parallel clocked latch circuit according to claim 8 wherein said level shifting means includes:

a resistor coupled between a second supply voltage terminal and said gate means.