Micro-power gain lattice

• US 5,041,797 A
• Filed: 11/19/1990
• Issued: 08/20/1991
• Est. Priority Date: 11/19/1990
• Status: Expired due to Term

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Nadler, Alexander J., Belcher, Donald K.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US07/615,248
• Time in Patent Office: 274 Days
• Field of Search: 330/70, 330/71, 330/310, 330/311, 330/293, 330/296
• US Class Current: 330/311
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/42 Amplifiers with two or more amplifying elements having their dc paths in series with the load, the control electrode of each element being excited by at least part of the input signal, e.g. so-called totem-pole amplifiers

Abstract

A broadband, high-gain RF signal amplifier which consumes a minimal amount of DC power has an input terminal to which an input signal to be amplified is coupled, and an output terminal from which an amplified output signal is derived. The signal amplifier has a plurality of first through n^th signal amplification stages coupled in cascade between the input terminal and the output terminal. Each stage comprises an amplifier device having an input electrode, an output electrode and a control electrode. The output electrode is coupled to an amplifier device of an i^th stage that is resistively coupled to the input electrode of the amplifier device of an (i+1)^th stage, and is DC coupled through a rectifier device to the control electrode of the amplifier device of the (i+1)^th stage. The control electrode of the amplifier device of the i^th stage is resistively coupled to the input electrode of the amplifier device of the (i+1)^th stage. The input terminal is coupled to the input electrode of the amplifier device of the first amplification stage, while the output terminal is coupled to the input electrode of the amplifier device of the n^th amplification stage.

Claims

1. A signal amplifier comprising:

an input terminal to which an input signal to be amplified is coupled;

an output terminal from which an amplified output signal is derived; and

a plurality of first through n^th signal amplification stages coupled in cascade between said input terminal and said output terminal, each stage comprising an amplifier device having an input electrode, an output electrode and a control electrode, the output electrode of an amplifier device of an i^th stage being resistively coupled to the input electrode of the amplifier device of an (i+1)^th stage, and being DC coupled through a rectifier device to the control electrode of said amplifier device of said (i+1)^th stage, the control electrode of said amplifier device of said i^th stage being resistively coupled to the input electrode of the amplifier device of said (i+1)^th stage; and

wherein

said input terminal is coupled to the input electrode of the amplifier device of said first amplification stage, and said output terminal is coupled to the input electrode of the amplifier device of said n^th amplification stage.

2. A signal amplifier according to claim 1, wherein a respective amplifier device comprises a bipolar transistor, having a base corresponding to its control electrode, an emitter corresponding to its input electrode and a collector corresponding to its output electrode.

3. A signal amplifier according to claim 1, wherein said rectifier device comprises at least one diode element coupled in series between the output electrode of an amplifier device of said i^th stage and the control electrode of an amplifier device of said (i+1)^th stage.

4. A signal amplifier according to claim 1, further comprising respective by-pass capacitors coupled between input electrodes respectively of amplifier devices of said plurality of amplifier stages and a reference potential terminal.

5. A multiple stage power amplifier comprising:

a first terminal to which a first voltage is applied;

a second terminal to which a reference voltage is applied;

a plurality of first through n^th amplifier stages coupled in cascade between said first and second terminals, each amplifier stage comprising a transistor having an emitter, a base and a collector, the collector of an i^th stage transistor being resistively coupled to the emitter of an (i+1)^th stage transistor and diode-coupled to the base of said (i+1)^th stage transistor, the base of said i^th stage transistor being resistively coupled to the emitter of said (i+1)^th stage transistor, the emitter of the first stage transistor being coupled to said second terminal, the collector of the n^th stage transistor being coupled to said first terminal;

an input terminal to which an input signal to be amplified is applied, coupled to the emitter of one of said stage transistors; and

an output terminal, from which an amplified output signal is derived, coupled to the emitter of another of said stage transistors.

6. A multi-stage amplifier according to claim 5, wherein said input terminal is coupled to the emitter of the first stage transistor and said output terminal is coupled to the emitter of the n^th stage transistor.