Integrated circuit with anti latch-up circuit in complementary MOS circuit technology

• US 5,041,894 A
• Filed: 06/19/1990
• Issued: 08/20/1991
• Est. Priority Date: 12/23/1987
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Siemens AG
• Inventors: Pribyl, Wolfgang, Reczek, Werner
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Deal, Cynthia S.
• Application Number:
  US07/477,929
• Time in Patent Office: 427 Days
• Field of Search: 357/41, 357/42, 357/21, 357/86, 307/296.2, 307/296.8
• US Class Current: 257/372
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Abstract

The risk of a latch-up is diminished by the incorporation of an additional bypass transistor between the output (OUT) and the supply voltage (V_DD) of an integrated circuit, for example a CMOS output stage. In case positive over-voltages that are greater than the sum of the supply voltage (V_DD) and the conducting-state voltage of the bypass transistor occur at the output (OUT), the bypass transistor becomes conductive and represents a low-impedance connection between the output (OUT) and the supply voltage (V_DD). In this case, the bypass transistor (BT) suctions additional charge carriers off and thereby increases the trigger current needed for the appearance of latch-up. The incorporation of an additional bypases transistor is possible both given well-shaped semiconductor zones that lie at a fixed potential as well as given well-shaped semiconductor zones that are wired to a variable potential. FIG. 1

Claims

1. Integrated circuit having anti latch-up circuit in complementary MOS circuit technology having a doped semiconductor substrate of a first conductivity type containing a first transistor with a channel of the first conductivity type and having a well-shaped semiconductor zone of a second conductivity type inserted in the doped semiconductor substrate containing a second transistor with a channel of the second conductivity type, the second transistor having a first terminal connected to a post and a second terminal connected to an output of the anti latch-up circuit, comprising the anti latch-up circuit containing a bypass transistor in the well-shaped semiconductor zone with a channel of the second conductivity type;

a gate terminal and a first terminal of the bypass transistor connected to the post and a second terminal of the bypass transistor connected to the output of the anti latch-up circuit.

2. Integrated circuit having anti latch-up circuit according to claim 1, wherein the bypass transistor is a p-channel field effect transistor;

wherein the doped semiconductor substrate of a first conductivity type is p-doped;

wherein the well-shaped semiconductor zone having a second conductivity type is n-doped; and

wherein the post and the well-shaped semiconductor zone of a second conductivity type are connected to a supply voltage.

3. Integrated circuit having anti latch-up circuit according to claim 1, wherein the bypass transistor is an n-channel field effect transistor;

wherein the doped semiconductor substrate of a first conductivity type is n-doped;

wherein the well-shaped semiconductor zone of a second conductivity type is p-doped; and

wherein the post and the well-shaped semiconductor zone of a second conductivity type are connected to ground.

4. Integrated circuit having anti latch-up circuit according to claim 1, wherein the bypass transistor is a p-channel field effect transistor;

wherein the doped semiconductor substrate of a first conductivity type is p-doped, and the well-shaped semiconductor zone of a second conductivity type is n-doped; and

wherein the post and the well-shaped semiconductor zone of a second conductivity type are connected to a variable supply voltage.

5. Integrated circuit having anti latch-up circuit according to claim 1, wherein the bypass transistor is an n-channel field effect transistor;

wherein the doped semiconductor substrate of a first conductivity type is n-doped;

wherein the well-shaped semiconductor zone of a second conductivity type is p-doped; and

wherein the post and the well-shaped semiconductor zone of a second conductivity type are connected to a variable supply voltage.

6. Integrated circuit having anti latch-up circuit according to claim 1, wherein the second terminal of the bypass transistor is realized by a semiconductor region that represents a terminal of a field effect transistor of the integrated circuit.

7. Integrated circuit having anti latch-up circuit according to claim 1, wherein the first terminal of the bypass transistor is realized by a stripe-shaped semiconductor zone of a first conductivity type and the second terminal is realized by a semiconductor zone of a first conductivity type surrounding a stripe-shaped semiconductor zone;

wherein a distance that corresponds to the width of a gate of a field effect transistor is present between the stripe-shaped semiconductor zone of a first conductivity type and the semiconductor zone of a first conductivity type; and

wherein the gate terminal is constructed with a gate material that is arranged in insulated fashion above the first and second terminal of the bypass transistor.

8. Integrated circuit having anti latch-up circuit in complementary MOS circuit technology having a doped semiconductor substrate of a first conductivity type containing a first transistor with a channel of the first conductivity type and having a well-shaped semiconductor zone of a second conductivity type inserted in the doped semiconductor substrate containing a second transistor with a channel of the second conductivity type, the second transistor having a first terminal connected to a post and a second terminal connected to an output of the anti latch-up circuit, comprising the anti latch-up circuit containing a bypass transistor in the well-shaped semiconductor zone with a channel of the second conductivity type;

a gate terminal and a first terminal of the bypass transistor connected to the post and a second terminal of the bypass transistor connected to the output of the anti latch-up circuit, the first terminal being a source terminal and the source terminal, the gate terminal and a substrate of the bypass transistor connected to a supply voltage via the post, the second terminal of the bypass transistor being a drain terminal of the bypass transistor, the drain terminal being connected to the output of the anti latch-up circuit.