Local area network with an active star topology comprising ring controllers having ring monitor logic function

• US 5,041,963 A
• Filed: 12/29/1988
• Issued: 08/20/1991
• Est. Priority Date: 12/29/1988
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Pollack, Frederick J., Ebersole, Ronald J.
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): Pappas, George C.
• Application Number:
  US07/291,700
• Time in Patent Office: 964 Days
• Field of Search: 364/200, 364/900, 370/85, 370/86, 370/60, 370/94.1
• US Class Current: 370/407
• CPC Class Codes: H04L 12/433 with asynchronous transmission, e.g. token ring, register insertion
• CPC Class Codes: H04L 12/44 Star or tree networks

Abstract

A star local area network includes a ring bus hub (4) capable of being connected to a plurality of nodes (3, 5, 9) geographically distant from the hub by means of low speed serial links (18, 19, 21, 28). The nodes include processor means (2, 30, 31) for creating messages for transfer on the network. A plurality of duplex communication links (18, 19, 21, 28) connect the nodes to the ring bus hub (4). The hub (40) is comprised of a plurality of ring controllers (10, 12, 14, 16) driven by a common clock source (7). Each ring controller is connected by means of a number of parallel lines to other ring controllers in series to form a closed ring. Each one (3) of the plurality of nodes is geographically distant from the hub (4) and is connected to a corresponding one (10) of the ring controllers by means of one (18, 19) of the duplex communication links. The node controllers including node interface means (40) for transmitting the messages as a contiguous stream of words on the duplex communication link. The ring controllers include ring bus interface means (42) for forming the messages into discrete data packets for insertion onto the ring bus and means (32, 34) for bufferring data messages received form the node and over the ring bus.

Claims

1. A star local area network, comprising:

a ring bus hub (4);

said ring bus hub (4) being comprised of a plurality of ring controllers (10, 12, 14,

     16) driven by a common clock source (7), each ring controller being connected by means of a ring bus (20, 22, 24,

     26) to other ring controllers in series to form a closed ring;

a plurality of nodes (3, 5,

     9) including processor means (2, 30,

     31) for creating messages for transfer on said network;

each one of said nodes including node controller means, and

a plurality of duplex communication links (18, 19, 21,

     28);

each one (3) of said plurality of nodes being geographically distant from said hub (4) and each one of said node controller means within a node being connected to a corresponding one (10) of said ring controllers by means of one (18,

     19) of said duplex communication links;

each of said node controllers including node interface means (40) for transmitting said messages as a contiguous stream of words on said duplex communication link;

each of said ring controllers including ring bus interface means (42) for forming said messages into discrete data packets for insertion onto said ring bus;

each one of said ring controllers including means (42) for buffering data packets and for inserting said data packets onto said ring bus;

one of said ring controllers (12) having ring monitor logic means for performing ring monitor functions to thereby designate said one ring controller as a ring monitor controller.

2. The combination in accordance with claim 1 wherein at least one of said plurality of duplex communication links (18, 19, 21, 28) includes:

an input data link (36);

an output data link (37);

an output buffer (32) connected to said input data link; and

,

an input buffer (34) connected to said output data link;

said input and output data links including means connected to said input buffer and to said output buffer for controlling data flow between said duplex communication link and said input buffer (34) and said output buffer (32).

3. The combination in accordance with claim 1 wherein at least one of said plurality of ring controllers (10, 12, 14, 16) includes:

a set of input pins (44);

a set of output pins (45);

a common logic connected to said ring bus interface logic (42);

said common logic including an output FIFO buffer (32) connected to an output link interface (36,

     37),

said common logic including an input FIFO buffer (34) connected to an input link interface (38), and,

mode selection means (43) for selecting a ring controller mode of operation;

said ring bus interface means (42) being responsive to said selection means (43) for activating said pins (44,

     46) with respect to said ring bus interface means (42).

4. The combination in accordance with claim 1 wherein at least one of said plurality of nodes (3, 5, 9) includes:

a set of input pins (44);

a set of output pins (45);

a common logic connected to said node interface logic (40);

said common logic including an output FIFO buffer (32) connected to an output link interface (36,

     37),

said common logic including an input FIFO buffer (34) connected to an input link interface (38), and,

mode selection means (43) for selecting a node controller mode of operation;

said node interface means (40) being responsive to said selection means (43) for activating said pins (44,

     46) with respect to said node interface means (40).

5. The combination in accordance with claim 2 wherein at least one of said plurality of ring controllers (10, 12, 14, 16) includes:

a set of input pins (44);

a set of output pins (45);

a common logic connected to said ring bus interface logic (42);

said common logic including an output FIFO buffer (32) connected to an output link interface (36,

     37),

said common logic including an input FIFO buffer (34) connected to an input link interface (38), and,

mode selection means (43) for selecting a ring controller mode of operation;

said ring bus interface means (42) being responsive to said selection means (43) for activating said pins (44,

     46) with respect to said ring bus interface means (42).

6. The combination in accordance with claim 2 wherein at least one of said plurality of node controller means includes:

a set of input pins (44);

a set of output pins (45);

a common logic connected to said node interface logic (40);

said common logic including an output FIFO buffer (32) connected to an output link interface (36,

     37),

said common logic including an input FIFO buffer (34) connected to an input link interface (38), and,

mode selection means (43) for selecting a node controller mode of operation;

said node interface means (40) being responsive to said selection means (43) for activating said pins (44,

     46) with respect to said node interface means (40.

7. The combination in accordance with claim 3 wherein at least one of said plurality of duplex communication links (18, 19, 21, 28) includes:

an input data link (36);

an output data link (37);

an output buffer (32) connected to said input data link; and

,

an input buffer (34) connected to said output data link;

said input and output data links including means connected to said input buffer and to said output buffer for controlling data flow between said duplex communication link and said input buffer (34) and said output buffer (32).

8. The combination in accordance with claim 7 wherein at least one of said plurality of node controller means includes:

a set of input pins (44);

a set of output pins (45);

a common logic connected to said node interface logic (40);

said common logic including an output FIFO buffer (32) connected to an output link interface (36,

     37),

said common logic including an input FIFO buffer (34) connected to an input link interface (38), and,

mode selection means (43) for selecting a node controller mode of operation;

said node interface means (40) being responsive to said selection means (43) for activating said pins (44,

     46) with respect to said node interface means (40).

9. The combination in accordance with claim 8 wherein at least one of said plurality of duplex communication links (18, 19, 21, 28) includes:

an input data link (36);

an output data link (37);

an output buffer (32) connected to said input data link; and

,

an input buffer (34) connected to said output data link;

said input and output data links including means connected to said input buffer and to said output buffer for controlling data flow between said duplex communication link and said input buffer (34) and said output buffer (32).

10. The combination in accordance with claim 4 wherein at least one of said plurality of ring controllers (10, 12, 14, 16) includes:

a set of input pins (44);

a set of output pins (45);

a common logic connected to said ring bus interface logic (42);

said common logic including an output FIFO buffer (32) connected to an output link interface (36,

     37),

said common logic including an input FIFO buffer (34) connected to an input link interface (38), and,

mode selection means (43) for selecting a ring controller mode of operation;

said ring bus interface means (42) being responsive to said selection means (43) for activating said pins (44,

     46) with respect to said ring bus interface means (42).