Method of forming an IC chip with self-aligned thin film resistors
First Claim
1. A process of forming an IC chip with at least one thin film resistor comprising:
- depositing a layer of thin film material on a predetermined area of a substrate;
depositing over said thin film material a layer of interconnect material arranged to establish electrically-conductive connection to the thin film material throughout said predetermined area thereof;
removing both said thin film and interconnect layers in predetermined regions of said area while leaving at least a part of the remaining layers aligned vertically, the remaining interconnect material defining an interconnect pattern for said IC chip;
said remaining part of said layers including at least one segment with thin film material to be developed as a resistor;
and removing all material above the layer of thin film material in an intermediate section of said one segment to present the exposed thin film material as a resistor between adjoining sections of said segment.
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Accused Products
Abstract
Process of making an IC chip with thin film resistors, and IC chips made by such process, wherein a chip substrate first is covered with layers of thin film and interconnect material (with an intermediate barrier layer if needed), such layers being etched away in predetermined regions in accordance with the metal interconnect pattern, the remaining layered material being aligned vertically, and thereafter, in a section of the remaining material, etching away the interconnect material (and barrier material if used) to expose the thin film material to form a thin film resistor which is self-aligned withe the adjoining sections of interconnect conductors. The material in the predetermined regions may be etched by a dry-etch (plasma) or by a wet-etch.
39 Citations
15 Claims
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1. A process of forming an IC chip with at least one thin film resistor comprising:
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depositing a layer of thin film material on a predetermined area of a substrate; depositing over said thin film material a layer of interconnect material arranged to establish electrically-conductive connection to the thin film material throughout said predetermined area thereof; removing both said thin film and interconnect layers in predetermined regions of said area while leaving at least a part of the remaining layers aligned vertically, the remaining interconnect material defining an interconnect pattern for said IC chip; said remaining part of said layers including at least one segment with thin film material to be developed as a resistor; and removing all material above the layer of thin film material in an intermediate section of said one segment to present the exposed thin film material as a resistor between adjoining sections of said segment. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A process of forming an IC chip with at least one thin film resistor comprising:
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depositing a layer of thin film material on a predetermined area of a substrate; depositing over said thin film material a layer of interconnect material arranged to establish electrically-conductive connection to the thin film material therebeneath; removing both said thin film and interconnect layers in predetermined regions of said predetermined area, the removal being carried out by a process which provides that the side edges of the remaining layers are aligned vertically, the remaining interconnect material defining an interconnect pattern for said IC chip; said remaining layers including at least one segment wherein at least part of the thin film material is to be developed as a resistor forming part of the circuit of said IC chip; and removing all material above the layer of thin film material in an intermediate section of said one segment to present the exposed thin film material without any interconnect directly thereabove, thereby to provide said resistor between spaced-apart sections of said one segment. - View Dependent Claims (12, 13, 14, 15)
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Specification