Metal oxide semiconductor device with well region

• US 5,043,779 A
• Filed: 07/23/1990
• Issued: 08/27/1991
• Est. Priority Date: 07/21/1989
• Status: Expired due to Fees

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Nishimura, Takeyoshi
• Primary Examiner(s): Mintel, William
• Assistant Examiner(s): Limanek, Robert P.
• Application Number:
  US07/557,178
• Time in Patent Office: 400 Days
• Field of Search: 357/23.4, 357/20, 357/23.8, 357/37, 357/38
• US Class Current: 257/339
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

An MOS device where the avalanche breakdown strength may be increased without decreasing the on-resistance of the device is provided by decreasing the width of a high impurity concentration area in contact with one of the two electrodes to increase the curvature of the deepest part of the well region.

Claims

1. A metal oxide semiconductor device comprising:

(a) a semiconductor substrate,

(b) a base area of a first conductivity type disposed on a first surface of the substrate,

(c) a plurality of structures disposed on and embedded in the base area, arranged in an equally spaced array contiguous with a first surface of the base area, each of which comprises;

(i) a channel area of a second conductivity type also contiguous with the first surface of the base area, wherein the spacing between two consecutive channel areas in immediately adjacent structures is less than the width of one of the channel areas,

(ii) a well region of the second conductivity type having a high impurity concentration relative to the channel area, disposed in the center of the channel area extending into the base area to a greater extent than the channel area,

(iii) an annular source area of the first conductivity type, located within the periphery of the channel area, said source area having an outer dimension less than that of the channel area, and extending into the base area to a lesser extent than that of the channel area,

(d) a gate through an insulating film disposed on the surface of each structure,

(e) a source electrode disposed on the surface of each structure, wherein the well region is a ring-shaped area surrounding the center of the channel area.

2. A device according to claim 1, wherein the spacing between two adjacent structures is approximately 70% the width of one channel area.