Non-volatile memory

• US 5,043,941 A
• Filed: 01/19/1990
• Issued: 08/27/1991
• Est. Priority Date: 01/30/1989
• Status: Expired due to Term

• Current Assignee: Kawasaki Microelectronics Incorporated (Megachips Corporation)
• Original Assignee: Kawasaki Steel Corporation (JFE Holdings Incorporated)
• Inventors: Sakamoto, Makoto
• Primary Examiner(s): Moffitt, James W.
• Application Number:
  US07/467,390
• Time in Patent Office: 585 Days
• Field of Search: 365/185, 365/189.05, 357/23.5
• US Class Current: 365/185.1
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits

Abstract

A non-volatile memory provides a signal hold circuit which uses a FAMOS instead of an input transistor of a ratiod inverting amplifier and outputs a change in a threshold value of the FAMOS, for the purpose of reducing the number of elements of the signal hold circuit. FAMOSs for programming and latching are provided respectively, and the FAMOSs are interconnected to each other at their floating gate electrodes to isolate the signal hold circuit and a program circuit and hence prevent a DC current path from being formed between those two circuits, for the purpose of miniaturization of a memory cell.

Claims

1. A non-volatile memory comprising:

a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply and;

a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region.

2. A non-volatile memory according to claim 1 wherein said programming field effect transistor additionally includes a switching element connected in series thereto.

3. A non-volatile memory according to claim 1, wherein the non-volatile memory is coupled to an integrated circuit.

4. An integrated circuit including a non-volatile memory, characterized in that the non-volatile memory comprises:

a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manners against the interruption of the power supply;

a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region.

5. A non-volatile memory comprising:

a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and

a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said latching field effect transistor and said programming field effect transistor being connected to each other at their control gate electrodes and being earthened at their source regions, the drain region of said latching field effect transistor being connected to a first terminal of said load element, said load element being connected to the power supply at a second terminal thereof different from said first terminal.

6. A non-volatile memory comprising:

a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and

a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said latching field effect transistor having a structure to prevent hot electrons from being produces in a channel region thereof.

7. A non-volatile memory comprising:

a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and

a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said latching field effect transistor having a structure to prevent hot electrons produces in a channel region thereof from being injected into the floating gate electrode thereof.

8. A non-volatile memory comprising:

a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and

a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said latching field effect transistor having a structure to reduce a leakage current produced between a source and the drain thereof or between the drain thereof and a body.

9. A non-volatile memory comprising:

a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and

a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said latching field effect transistor being of an LDD structure which has second conductivity type regions with lower concentration than second conductivity type source and drain regions on the surface of a first conductivity type substrate making contact with the channel region thereof.

10. A non-volatile memory comprising:

a signal hold circuit including at least an electrically programmable field effect transistor provided with a latching floating gate electrode and a load element, said signal hold circuit being operational to amplify the threshold voltage of said latching field effect transistor by exerting a power supply voltage on a control gate electrode of said latching field effect transistor, said signal hold circuit further holding a binary signal in a non-volatile and fully static manner against the interruption of the power supply; and

a program circuit including at least a programming field effect transistor provided with a floating gate electrode, said floating gate electrode being connected at least to said floating gate electrode of said latching field effect transistor of said signal hold circuit, said program circuit having no DC current path between itself and said signal hold circuit and writing any information in a drain region of said programming field effect transistor by exerting a program voltage on said drain region, said signal hold circuit additionally including a capacitor for assisting an information storing action between a signal hold node and the ground.