Analog to digital conversion on multiple channel IC chips

• US 5,045,685 A
• Filed: 06/06/1990
• Issued: 09/03/1991
• Est. Priority Date: 03/27/1989
• Status: Expired due to Term

• Current Assignee: Irvine Sensors Corp.
• Original Assignee: Irvine Sensors Corp.
• Inventors: Wall, Llewellyn E.
• Primary Examiner(s): Nelms, David C.
• Application Number:
  US07/534,969
• Time in Patent Office: 454 Days
• Field of Search: 250/208.1, 250/208.2, 250/211 J, 250/211 R, 250/214 R, 250/209, 357/30 H
• US Class Current: 250/208.1
• CPC Class Codes: H01L 25/043 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03M 1/123 Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
• CPC Class Codes: H03M 1/56 Input signal compared with linear ramp
• CPC Class Codes: H03M 1/58 Non-linear conversion

Abstract

An integrated circuit chip having a plurality of parallel channels, and a stack of such chips, are disclosed, in which the function of A/D signal conversion is accomplished in each on-chip channel. In order to satisfy the power and real estate limitations of the chip(s), a substantial part of the A/D conversion circuitry is located off-chip. Two devices are required in each channel on each chip, a precision comparator, and a storage register. These may be combined with an off-chip analog ramp, and an off-chip digital ramp. Certain on-chip performance enhancements are disclosed, which can operate either in the analog mode or the digital mode. One such enhancement is compensating for the voltage offset of each comparator. Another enhancement is reducing the duty cycle of each precision comparator, in order to lower power requirements. An important use for the disclosed concepts is the field of multi-layer Z-technology modules, having two dimensional photo-detector arrays.

Claims

1. In an electronic system containing a densely packaged three-dimensional structure which includes circuitry for obtaining and processing analog photodetector signals, such structure (a) being formed by a plurality of stacked circuitry-carrying layers, each having a plurality of parallel signal channels, and (b) having a two-dimensional array of photodetectors located on one surface of the structure, each in contact with a separate signal channel;

analog to digital conversion circuitry comprising;

a comparator in each channel having two analog signal inputs and one digital output, one of its input signals being received from the photodetector in the same channel;

a storage register in each channel adapted to receive and store digital values;

an analog voltage ramp generator which has its analog output connected to one input of each comparator in each of a plurality of channels;

a counter which develops a changing digital value incrementally proportional to the simultaneous analog signal of the ramp generator, and which has its output connected to each storage register in each of a plurality of channels;

each comparator being so arranged that its output changes from one digital value to the other when its two analog voltage inputs reach substantial equality; and

the connection of each comparator to the same channel storage register being such that the storage register maintains the specific output counter value existing at the time of change of the output signal of the same channel comparator.

2. The electronic system of claim 1 in which the analog voltage ramp generator is located outside the three-dimensional structure.

3. The electronic system of claim 1 in which the counter is located outside the three-dimensional structure.

4. The electronic system of claim 2 in which the counter is located outside the three-dimensional structure.

5. The electronic system of claim 1 in which;

the three-dimensional structure is located in a low temperature environment; and

the analog ramp and counter are located in a higher temperature environment.

6. The electronic system of claim 1 which also comprises:

error compensating means for adjusting the comparator channel signal to compensate for the voltage offset error of the comparator.

7. The electronic system of claim 6 in which an error compensating means is included in each channel.

8. The electronic system of claim 4 which also comprises:

error compensating means for adjusting the comparator channel signal to compensate for the voltage offset error of the comparator.

9. The electronic system of claim 8 in which an error compensating means is included in each channel.

10. The electronic system of claim 1 which also comprises:

power reducing means for causing the duty cycle of the comparator to constitute only a small fraction of a full duty cycle.

11. The electronic system of claim 10 in which a power reducing means is included in each channel.

12. The electronic system of claim 4 which also comprises:

power reducing means for causing the duty cycle of the comparator to constitute only a small fraction of a full duty cycle.

13. The electronic system of claim 12 in which a power reducing means is included in each channel.

14. The electronic system of claim 8 which also comprises:

power reducing means for causing the duty cycle of the comparator to constitute only a small fraction of a full duty cycle.

15. The electronic system of claim 14 in which an error compensating means and a power reducing means are included in each channel.

16. An electronic system containing an array of analog signal generators, and adjacent parallel channels for such analog signals;

a comparator in each channel having two analog signal inputs and one digital output, one of its input signals being received from the signal generator in the same channel;

a storage register in each channel adapted to receive and store digital values;

an analog voltage ramp generator which has its analog output connected to one input of each comparator in each of a plurality of channels;

a counter which develops a changing digital value incrementally proportional to the simultaneous analog signal of the ramp generator, and which has its output connected to each storage register in each of a plurality of channels;

each comparator being so arranged that its output changes from one digital value to the other when its two analog voltage inputs reach substantial equality; and

the connection of each comparator to the same channel storage register being such that the storage register maintains the specific counter output value existing at the time of change of the output signal of the same channel comparator.

17. The electronic system of claim 16 in which:

the parallel channels are located on an integrated circuit chip; and

the voltage ramp generator and counter are located elsewhere.

18. The electronic system of claim 17 in which the integrated circuit chip is located inside a cooled structure.

19. The electronic system of claim 16 which also comprises:

error compensating means for adjusting the comparator channel signal to compensate for the voltage offset error of the comparator.

20. The electronic system of claim 19 in which an error compensating means is included in each channel.

21. The electronic system of claim 16 which also comprises:

power reducing means for causing the duty cycle of the comparator to constitute only a small fraction of a full duty cycle.

22. The electronic system of claim 21 in which a power reducing means is included in each channel.

23. The electronic system of claim 16 in which an error compensating means and a power reducing means are included in each channel.

24. The electronic system of claim 17 which also comprises:

error compensating means for adjusting the comparator channel signal to compensate for the voltage offset error of the comparator.

25. The electronic system of claim 24 in which an error compensating means is included in each channel.

26. The electronic system of claim 17 which also comprises:

power reducing means for causing the duty cycle of the comparator to cinstitute only a small fraction of a full duty cycle.

27. The electronic system of claim 26 in which a power reducing means is included in each channel.

28. The electronic system of claim 17 in which an error compensating means and a power reducing means are included in each channel.

29. The electronic system of claim 18 which also comprises:

error compensating means for adjusting the comparator channel signal to compensate for the voltage offset error of the comparator.

30. The electronic system of claim 29 in which an error compensating means is included in each channel.

31. The electronic system of claim 18 which also comprises:

power reducing means for causing the duty cycle of the comparator to cinstitute only a small fraction of a full duty cycle.

32. The electronic system of claim 31 in which a power reducing means is included in each channel.

33. The electronic system of claim 18 in which an error compensating means and a power reducing means are included in each channel.

34. In an electronic system having an array of analog signal generators, integrated circuitry immediately adjacent to such signal generators, and additional non-adjacent processing circuitry, the method of enhancing the efficiency of the electronic system which comprises:

including in the integrated circuitry a plurality of parallel channels, each receiving an incoming analog signal from a separate signal generator, and each containing a comparator and a storage register;

inputting the analog signal in each channel to one input of the comparator in the same channel;

inputting an analog ramp generator signal to the other input of each comparator;

emitting an output signal from each comparator when its input signals reach equality;

changing the digital value in each of the storage registers by inputting to them a changing value from a counter, such changing value being incrementally proportional to the analog ramp generator signal; and

using the output signal of each comparator to capture and hold the digital value in the same channel storage register.

35. The method of claim 34 in which the analog ramp generator and the counter are included in the non-adjacent processing circuitry.