Topographic pattern delineated power MOSFET with profile tailored recessed source

• US 5,045,903 A
• Filed: 11/16/1989
• Issued: 09/03/1991
• Est. Priority Date: 05/17/1988
• Status: Expired due to Term

• Current Assignee: Microsemi Corporation (Microchip Technology Incorporated)
• Original Assignee: Advanced Power Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Meyer, Theodore O., Pike, Douglas A. Jr., Mosier, John W. II, Tsang, Dah W., Hollinger, Theodore G.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): FAHMY, WAEL M
• Application Number:
  US07/439,101
• Time in Patent Office: 656 Days
• Field of Search: 357/23.4, 357/23.8, 357/23.3, 357/55
• US Class Current: 257/339
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O₂ -SF₆ plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.

Claims

1. A self-aligned vertical double-diffused insulated gate transistor, comprising:

a silicon substrate with doping of a first dopant type and having an upper surface,

an oxide layer on he upper surface of the substrate,

an opening in the oxide layer having a defined outline characteristic,

a trench having sidewalls and a base formed in the substrate within the opening,

double-diffused dopant means of opposite second and first dopant types disposed within the substrate defining first and second P-N junctions spaced laterally apart under the oxide layer and contoured in accordance with the defined outline characteristic, the P-N junctions being arranged to define a field effect transistor including a source region of the first dopant type, the source region being formed in he substrate along the trench sidewalls subjeacent the defined outline characteristic and bounded by the first P-N junction, a drain of the first dopant type bounded by the second P-N junction and spaced laterally from the defined outline characteristic and extending downward into the substrate, and a region of the second dopant type defining a conduction channel extending between the first and second P-N junctions along the oxide layer at the upper surface of the substrate operable upon inversion to conduct current between the source and drain, and

a gate conductive layer on the oxide layer insulated from the conduction channel and a source conductive layer on the upper surface of the substrate within said opening, the source conductive layer being deposited in the trench and thereby spaced below the gate conductive layer so that the conductive layers are electrically separate,

the dopant means being introduced to the substrate via the upper surface thereof prior to forming the trench so that the substrate silicon underlying the source conductive layer is substantially defect free.

and the region of the second dopant type including a first portion alongisde the source region having a first doping concentration and a second portion contained within the first portion and extending laterally beneath the source region and the source conductive layer and having a second doping concentration greater than the first doping concentration for withstanding reverse-bias avalanche current flow.

2. A device according to claim 1 including insulative sidewall spacers extending along the defined outline characteristic atop the oxide layer and laterally separating the gate and source conductive layers.

3. A device according to claim 1 in which the gate conductive layer includes a doped polysilicon layer in contact with the gate oxide layer and a metal layer atop the doped polysilicon layer.

4. A device according to claim 1 including a low-resistivity contact layer extending between the source region and the source conductive layer.

5. A device according to claim 1, in which the dopant means was ion implanted in the substrate prior to forming the trench.

6. A self-aligned vertical double-diffused insulated gate transistor, comprising:

a silicon substrate with doping of a first dopant type and having an upper surface,

an oxide layer on the upper surface of the substrate,

an opening in the oxide layer having a defined outline characteristic,

a trench having sidewalls and a base formed in the substrate within the opening,

double-diffused dopant means of opposite second and first dopant types disposed within the substrate defining first and second P-N junctions spaced laterally apart under the oxide layer and contoured in accordance with the defined outline characteristic, the P-N junctions being arranged to define a field effect transistor including a source region of the first dopant type, the source region being formed in the substrate along the trench sidewalls subjacent the defined outline characteristic and bounded by the first P-N junction, a drain of the first dopant type bounded by the second P-N junction and spaced laterally from the defined outline characteristic and extending downward into the substrate, and a region of the second dpant type defining a conduction channel extending between the first and second P-N junctions along the oxide layer at the upper surface of the substrate operable upon inversion to conduct current between the source and drain,

a gate conductive layer on the oxide layer insulated from the conduction channel and a source conductive layer on the upper surface of the substrate within said opening, the source conductive layer being deposited in the trench and thereby spaced below the gate conductive layer so that the conductive layers are electrically separate, and

insulative sidewall spacers extending along the defined outline characteristic atop the oxide layer and laterally separating the gate and source conductive layers.

7. A self-aligned vertical double-diffused insulated gate transistor, comprising:

a silicon substrate with doping of a firt dopant type and having an upper surface,

an oxide layer on the upper surface of the substrate,

an opening in the oxide layer having a defined outline characteristic,

a trench having sidewalls and a base formed in the substrate within the opening,

double-diffused dopant means of opposite second and first dopant types disposed within the substrate defining first and second P-N junctions spaced laterally apart under the oxide layer and contoured in accordance with the defined outline characteristic, the P-N junctions being arranged to define af ield effect transistor including a source region of the first dopant type, the source region being formed in the substrate along the trench sidewalls subjacent the defined outline characteristic and bounded by the first P-N junction, a drain of the first dopant type bounded by the second P-N junction and spaced laterally from the defined outline characteristic and extending downward into the substrate, and a region of the second dopant type defining a conduction channel extending between the first and second P-N junctions along the oxide layer at the upper surface of the substrate operable upon inversion to conduct current between the source and drain,

a gate conductive layer insulated from the conduction channel including a doped polysilicon layer in contact with the oxide layer and a metal layer atop the doped polysilicon layer, and

a source conductive layer on the upper surface of the substrate within said opening, the source conductive layer being deposited in the trench and thereby spaced below the gate conductive layer so that the conductive layers are electrically separate.

8. A self-aligned vertical double-diffused insulated gate transistor, comprising:

a silicon substrate with doping of a first dopant type and having an upper surface,

an oxide layer on the upper surface of the substrate,

an opening in the oxide layer having a defined outline characteristic,

a trench having sidewalls and a base formed in the substrate within the opening,

double-diffused dopant means of opposite second and first dopant types disposed within the substrate defining first and second P-N junctions spaced laterally apart under the oxide layer and contoured in accordance with the defined outline characteristic, the P-N junctions being arranged to define a field effect transistor including a source region of the first dopant type, the source region being formed in the substrate along the trench sidewalls, subjacent the defined outline characteristic and bounded by the first P-N junction, a drain of the first dopant type bounded by the second P-N junction and spaced laterally from the defined outline characteristic, and a region of the second dopant type defining a conduction channel extending between the first and second P-N junctions along the oxide layer at the upper surface of the substrate operable upon inversion to conduct current between the source and drain, and

a gate conductive layer on the oxide layer insulated from the conduction channel and a source conductive layer on the upper surface of the substrate within said opening, the source conductive layer being deposited in the trench, the trench sidewalls having a stairstep profile including a vertical lower portion extending to the trench base, and the source conductive layer contacting the trench base and the vertical lower portion of the stairstepped sidewalls.

9. A device according to claim 8 in which the source conductive layer is confined within the trench and the gate conductive layer is confined within the sidewall spacers, the transistor having an open topography such that all regions of the source are electrically contiguous within the substrate without overlap of the gate and source conductive layers.

10. A device according to claim 8 in which the source and gate conductive layers include metal layers.

11. A device according to claim 8 including an insulative sidewall spacer extending along the defined outline characteristic atop the oxide layer and laterally separating the gate and source conductive layers.

13. A device according to claim 11 in which the gate conductive layer include a doped polysilicon layer in contact with the oxide layer and a metal layer atop the doped polysilicon layer.

12. A device according to calim 11 in which the trench sidewalls include an upper portion which is recessed beneath the insulative sidewall spacer.

14. A device according to claim 12 including a low-resistivity contact layer extending between the source region and the source conductive layer.

15. A device according to claim 14 in which the low-resistivity contact layer is a shallow diffusion of the same dopant type as the source region.

16. A device according to claim 14 in which the low-resistivity contact layer is a layer of one of a refractory metal and a metal silicide.