Data processor

• US 5,045,997 A
• Filed: 10/28/1988
• Issued: 09/03/1991
• Est. Priority Date: 12/03/1987
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Watanabe, Akira
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): Chun, Debra A.
• Application Number:
  US07/264,056
• Time in Patent Office: 1,040 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/158
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence

Abstract

The efficiency of a processor in which a packet is stored in a receiver buffer, processed in a central processing unit, and sent out via a transmitter buffer, is low. According to the invention, data is transferred to a high-speed memory via the receiver memory. When the high-speed memory is filled with data, the data is processed by the CPU, and the packet is transmitted from the high-speed memory via the transmitter memory. A competition control section is provided to control data accesses in the sequential operation.

Claims

1. A data processor to be connected to another data processor via a bus for transmitting or receiving data to execute a predetermined process, which comprises:

(a) a central processing unit;

(b) a high-speed memory; and

(c) a memory competition circuit, said memory competition circuit including;

(i) an input data memory connected to said bus for temporarily storing data to be input to said high-speed memory from said bus;

(ii) an output data memory connected to said high-speed memory for temporarily storing data to be output to said bus from said high-speed memory;

(iii) a read register connected to said high-speed memory for temporarily latching data read out of said high-speed memory by said central processing unit;

(iv) a write register connected to said central processing unit for temporarily latching data to be written in said high-speed memory by said central processing unit;

(v) a competition control section connected to said input and output data memories and said central processing unit for receiving a write request from said input data memory, a read request from said output data memory, a read request from said central processing unit, and a write request from said central processing unit to execute access to said high-speed memory by said requests according to a predetermined priority order among said input data memory, output data memory, read register and write register, or issuing a wait signal to said central processing unit when access is not in time,

(vi) a clock generator for generating a clock signal independent of that of said central processing unit;

(vii) a synchronizing circuit connected to said clock generator for synchronizing access requests to be input to said memory competition circuit; and

(viii) an arbiter connected to said synchronizing circuit for selecting a request of the highest priority to control competition among said access requests for access to said high-speed memory.

2. The data processor of claim 1, wherein said memory competition circuit comprises:

a receiver counter;

a transmitter counter; and

means responsive to a count signal from said receiver or transmitter counter to manage addresses within said high-speed memory and switches an area of said high-speed memory between receiver and transmitter buffers for controlling transmission and reception between said input or output data memory and said high-speed memory.