Wiring design for semiconductor integrated circuit

• US 5,046,017 A
• Filed: 12/21/1988
• Issued: 09/03/1991
• Est. Priority Date: 12/23/1987
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd., Hitachi Microcomputer Engineering Limited
• Original Assignee: Hitachi, Ltd., Hitachi Microcomputer Engineering Limited
• Inventors: Nishizawa, Kouichi, Yuyama, Kyoji
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Trans, V. N.
• Application Number:
  US07/287,059
• Time in Patent Office: 986 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/113
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method of designing semiconductor integrated circuits wherein rough routes are designated after a process of design for cells layout is completed, then wirings between cells are supposed automatically on the basis of the designated rough routes, investigation of the characteristic of the wirings is executed, and after a target characteristic is attained, a wiring pattern satisfying all of required electrical and physical conditions, including layout rules, i.e. a detailed wiring pattern, is prepared.

Claims

1. A method of designing a semiconductor integrated circuit device comprising the steps of:

positioning a first circuit block in said semiconductor integrated circuit device;

positioning a signal terminal on said first circuit block;

positioning a second circuit block in said semiconductor integrated circuit device;

positioning a signal terminal on said second circuit block;

positioning a first partial wiring which constitutes only a portion of a first wiring to be formed in said semiconductor integrated circuit device for connecting said signal terminal of said first circuit block and said signal terminal of said second circuit block; and

estimating characteristics of said first wiring based on position information of said terminal of said first circuit block, position information of said terminal of said second circuit block, and position information of said first partial wiring.

2. A method according to claim 1, further comprising the steps of:

positioning a second partial wiring which constitutes only a portion of a second wiring to be formed in said semiconductor integrated circuit device for connecting said signal terminal of said first circuit block and said signal terminal of said second circuit block; and

estimating characteristics of said second wiring based on position information of said signal terminal of said first circuit block, position information of said signal terminal of said second circuit block, and position information of said second partial wiring.

3. A method according to claim 1, further comprising the step of:

positioning said first wiring based on position information of said terminal of said first circuit block, position information of said terminal of said second circuit block, and position information of said first partial wiring when a result of the estimating of the characteristics of said first wiring attains a predetermined value.

4. A method according to claim 1, wherein:

the step of positioning said first circuit block includes the steps of displaying and positioning a graphic representation of said first circuit block on a display device;

the step of positioning said signal terminal of said first circuit block includes the steps of displaying and positioning a graphic representation of said signal terminal of said first circuit block on the display device;

the step of positioning said second circuit block includes the steps of displaying and positioning a graphic representation of said second circuit block on the display device;

the step of positioning said signal terminal of said second circuit block includes the steps of displaying and positioning a graphic representation of said terminal of said second circuit block on the display device;

the step of positioning said first partial wiring includes the steps of displaying and positioning a graphic representation of said first partial wiring on the display device; and

the estimating step comprises the step of estimating characteristics of said first wiring based on position information of said graphic representation of said signal terminal of said first circuit block, position information of said graphic representation of said signal terminal of said second circuit block, and position information of said graphic representation of said first partial wiring.

5. A method of designing a semiconductor integrated circuit device comprising the steps of:

positioning a first circuit block in said semiconductor integrated circuit device;

positioning a signal terminal on said first circuit block;

positioning a second circuit block in said semiconductor integrated circuit device;

positioning a signal terminal on said second circuit block;

positioning a first partial wiring and a second partial wiring, each of said first partial wiring and said second partial wiring constituting only a portion of a first wiring to be formed in said semiconductor integrated circuit device for connecting said signal terminal of said first circuit block and said signal terminal of said second circuit block; and

estimating characteristics of said first wiring based on position information of said signal terminal of said first circuit block, position information of said signal terminal of said second circuit block, position information of said first partial wiring, and position information of said second partial wiring.

6. A method according to claim 5, further comprising the step of:

positioning said first wiring based on position information of said terminal of said first circuit block, position information of said terminal of said second circuit block, position information of said first partial wiring, and position information of said second partial wiring.

7. A method according to claim 5, wherein:

the step of positioning said first circuit block includes the steps of displaying and positioning a graphic representation of said first circuit block on a display device;

the step of positioning said signal terminal of said first circuit block includes the steps of displaying and positioning a graphic representation of said signal terminal of said first circuit block on the display device;

the step of positioning said second circuit block includes the steps of displaying and positioning a graphic representation of said second circuit block on the display device;

the step of positioning said signal terminal of said second circuit block includes the steps of displaying and positioning a graphic representation of said terminal of said second circuit block on the display device;

the step of positioning said first partial wiring and said second partial wiring includes the steps of displaying and positioning graphic representations of said first partial wiring and said second partial wiring on the display device; and

the estimating step comprises the step of estimating characteristics of said first wiring based on position information of said graphic representation of said signal terminal of said first circuit block, position information of said graphic representation of said signal terminal of said second circuit block, and position information of said graphic representations of said first partial wiring and said second partial wiring.

8. A method of designing a semiconductor integrated circuit device comprising the steps of:

positioning a first circuit in said semiconductor integrated circuit device;

positioning a signal terminal on said first circuit;

positioning a second circuit in said semiconductor integrated circuit device;

positioning a signal terminal on said second circuit;

positioning a first straight-shaped partial wiring which constitutes only a portion of a first wiring to be formed in said semiconductor integrated circuit device for connecting said signal terminal of said first circuit and said signal terminal of said second circuit; and

estimating resistance characteristics of said first wiring based on position information of said terminal of said first circuit, position information of said terminal of said second circuit, and position information of said first straight-shaped partial wiring.

9. A method according to claim 8, wherein:

the step of positioning said first circuit includes the steps of displaying and positioning a graphic representation of said first circuit on a display device;

the step of positioning said signal terminal of said first circuit includes the steps of displaying and positioning a graphic representation of said signal terminal of said first circuit on the display device;

the step of positioning said second circuit includes the steps of displaying and positioning a graphic representation of said second circuit on the display device;

the step of positioning said signal terminal of said second circuit includes the steps of displaying and positioning a graphic representation of said signal terminal of said second circuit on the display device;

the step of positioning said first straight-shaped partial wiring includes the steps of displaying and positioning a graphic representation of said first straight-shaped partial wiring on the display device; and

the estimating step comprises the step of estimating resistance characteristics of said first wiring based on position information of said graphic representation of said terminal of said first circuit, position information of said graphic representation of said terminal of said second circuit, and position information of said graphic representation of said first straight-shaped partial wiring.