System for transferring test program information

• US 5,046,033 A
• Filed: 08/09/1989
• Issued: 09/03/1991
• Est. Priority Date: 08/09/1989
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Shea, Dean J., Hackney, Gregory P., Andreasen, David A.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Ramirez, Ellis B.
• Application Number:
  US07/391,075
• Time in Patent Office: 755 Days
• Field of Search: 364/578, 364/579, 364/580, 364/200, 364/900, 371/23, 371/27
• US Class Current: 702/119
• CPC Class Codes: G01R 31/318307 computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging

Abstract

The present system is employed to generate and transmit information which is needed to construct or assemble truth tables and pertinent data which are directed to associated circuits which require testing. The present method employs a technique whereby information is nested, or compacted, in accordance with certain rules of grammar and is transmitted from a circuit design group to a vendor, i.e., a manufacturer of the circuit designed by a design group. When the nested information is expanded by a translator device, or by a translation program, at the manufactuer'"'"'s location, it is directly expandable into truth table information for use by various logic testers. Each of the truth tables defines a specific function that the designer wants tested in the associated circuit. The manufacturer supplies the test platform hardware which generates the desired signal patterns defined by the truth table information and pertinent data. The present method is employed to more efficiently compact and transmit information which is ultimately translated into truth table and test data information to effect a test program for various test platforms. By way of example, in the present description, the circuit to which the compacted information is applicable is a hybrid semiconductor multicircuit package and the test information relates to test of the semiconductor chips in wafer form as well as the chips before and after being mounted in package form.

Claims

1. A system for transmitting information from a source of designing electrical circuits to a source of manufacturing electrical circuits, which information is used in testing an electrical circuit at said source of manufacturing electrical circuits, comprising in combination:

electric circuit design means formed to design at least one particular circuit;

autogeneration means connected to said electrical circuit design means to receive information therefrom related to said particular circuit, said autogeneration means formed to create a compacted information program including truth table concepts, related to said particular circuit, whereby when said information program is implemented said truth table concepts cause certain aspects of said particular circuit to be tested;

information communication means having first and second stations with said first station connected to said autogeneration means to receive said compacted information program therefrom, said first station formed to transmit said compacted information program to said second station;

translation means connected to said second station to receive said compacted information program therefrom, said translation means formed to expand said compacted information program into said truth table concepts; and

testing means connected to said translation means to receive said truth table concepts and formed to apply signals representing said truth table concepts to said particular circuit to effect testing thereof.

2. A system according to claim 1 whereby said autogeneration means includes memory means having raw information stored therein and electronic data processing means, and wherein said raw information includes a set of grammar rules which act to compact and define concepts, which concepts direct said testing means to employ certain signals to effect testing of said particular circuit.

3. A system according to claim 2 wherein said raw information further includes waveform information, which waveform information acts to cause certain waveform signals to be applied in said testing means to effect testing of said particular circuit.

4. A system according to claim 2 wherein said raw information further includes information about circuit pins of said particular circuit and which information about circuit pins further provides the basis for having signals applied to said circuit pins to effect certain electrical test aspects of said particular circuit.

5. A system according to claim 2 wherein said raw information further includes information related to timing signals, which information related to timing signals provides a basis for generating and applying timing aspects to signals applied to said particular circuit to effect testing certain aspects of said particular circuit.

6. A system according to claim 1 wherein said autogeneration means has first and second electronic data processing means and wherein said raw information is manipulated in said first electronic data processing means to provide a set of header concepts and wherein said second electronic data processing means is formed to employ said header concepts to generate a set of vector concepts to provide truth table concepts to be applied to said testing means.

7. A system according to claim 6 wherein said header concepts include a first set of information concepts and wherein said header concepts further include group information concepts, which group information concepts comprise certain of said first set of information concepts as well as a group identifier.

8. A system according to claim 7 wherein said header information further includes MACRO instructions and wherein said MACRO instructions are formed to include group identifiers as well as other MACRO instructions.

9. A method for translating compacted information related to testing at least one circuit means, which one circuit means includes logic circuits and which one circuit means is formed to have a plurality of input means available for signals to be applied thereto and formed to have a plurality of output means available to have signals read therefrom, comprising the steps of:

a) defining and generating, in machine readable language, a plurality of first phase signal concepts which are available to be employed to expand a compacted information program, and which first phase signal concepts include timing concepts, waveform concepts, and circuit hardware identifiers;

b) defining and generating, in machine readable language, a plurality of group identifiers each of which represents a different collection of said first phase signal concepts;

c) defining and generating, in machine readable language, a plurality of MACRO instructions each of which represents a different collection of group identifiers and alternatively a different collection of group identifiers plus other MACRO instructions; and

d) defining and generating, in machine readable language, a plurality of different sets of vector signal concepts with each different set of vector signal concepts including selected ones of said MACRO instruction concepts.

10. A method for transferring information related to testing at least one circuit means, which one circuit means includes logic circuits and which one circuit means is formed to have a plurality of input means available for signals to be applied thereto and formed to have a plurality of output means available to have signals read therefrom, comprising the steps of:

a) defining and generating, in machine readable language, a plurality of different waveforms to be used for application to selected ones of said input means and with each of said different waveforms having a different first identifier;

b) defining and generating in machine readable language at least one cycle time in which certain test signals are applied;

c) defining and generating, in machine readable language, different second identifiers each of which represents a different one of said input means to which certain signals may be applied;

d) defining and generating, in machine readable language, different third identifiers each of which represents a different one of said output means from which signals may be read;

e) defining and generating, in machine readable language, at least a fourth identifier for a particular one of said input means to have clock signals applied thereto;

f) defining and generating, in machine readable language, different fifth identifiers each of which represents a different one of said logic circuits to which signals may be applied;

g) defining and generating, in machine readable language, different first groups of associated signals with each of said first groups of associated signals having different sixth identifiers and with each of said first groups of associated signals including related ones of said first identifiers as well as others of said identifiers.

h) defining and generating, in machine readable language, different second groups of associated signals with each of said second groups of associated signals having different seventh identifiers and with each of said second groups of associated signals including related ones of said second identifiers;

i) defining and generating, in machine readable language, at least third groups of associated signal concepts which defines certain logic circuits and which has an eighth identifier;

j) defining and generating, in machine readable language, a plurality of different MACRO instructions with each of said different MACRO instructions having a different ninth identifier and each MACRO instruction having selected different ones of said sixth, seventh and eighth identifiers; and

k) defining and generating, in machine readable language, a plurality of different sets of vector signal concepts with each different set of vector signal concepts including selected ones of said ninth identifiers which in turn expand into sixth, seventh, and eighth identifiers which in turn expand into information signals, represented by said first, second, third, fourth and fifth identifiers to effect a test of said circuit means.

11. A system for preparing compacted test information, at a site for designing high density electrical circuits, for use at a site for manufacturing electrical circuits, which test information is used in testing electrical circuits at said site for manufacturing electrical circuits, comprising in combination:

CAD electric circuit design means formed to design at least one particular multicircuit;

autogeneration means connected to said CAD electrical circuit design means to receive information therefrom related to said particular multicircuit, said autogeneration means formed to create a compacted test information program including truth table concepts in compacted vector format related to said particular circuit, whereby said test information program is directly decodable into said truth table concepts, in machine readable form, for use by a predetermined test platform to test certain aspects of said particular circuit to be tested,

memory means adapted for receiving and storing said compacted test information,

translation means adapted to be coupled to said memory means to receive said compacted test information program therefrom, said translation means formed to expand said compacted test information program into said truth table concepts, and to decode test procedures usable by said predetermined test platform, and

test platform means connected to said translation means to receive said truth table concepts and said test procedures and formed to apply signals representing said truth table concepts and said test procedures to said particular multicircuit to effect testing thereof.

12. In a system for preparing compacted test information for use at a site for manufacturing electrical circuits, which test information is used in testing electrical circuits at said site for manufacturing electrical circuits, comprising in combination:

memory means for storing compacted test information,

said memory means containing header information and truth table concepts information in vector formats and machine readable form,

translator means connected to said memory means for receiving said compacted test information in machine readable form,

said translator means comprising scanner means coupled to said memory means for decoding and expanding said compacted test information, and

test platform means coupled to said translator means for receiving said decoded expanded test information.

13. In a system according to claim 12 wherein said translator further comprises parser means coupled to said scanner means.

14. In a system according to claim 13 wherein said translator means further comprises vector view logic means.

15. In a system according to claim 14 wherein said translator means further comprises a plurality of operation procedures means cyclically coupled to said vector view logic means.

16. In a system according to claim 15 wherein said translator means further comprises calling program means coupled to said operational procedure means for activating said operational procedures.

17. In a system according to claim 16 wherein said translator means further includes symbol table means coupled to said vector view logic means and associated ones of said operational procedure means.