Pipeline image processor

• US 5,046,190 A
• Filed: 09/06/1988
• Issued: 09/03/1991
• Est. Priority Date: 09/06/1988
• Status: Expired due to Term

• Current Assignee: Allen-Bradley Company Milwaukee WI
• Original Assignee: Allen-Bradley Company (Rockwell Automation, Inc.)
• Inventors: Daniel, Thomas, Ortais, Paul
• Primary Examiner(s): Moore, David K.
• Assistant Examiner(s): Couso, Jose L.
• Application Number:
  US07/240,523
• Time in Patent Office: 1,092 Days
• Field of Search: 364/130, 364/137, 364/138, 382/27, 382/41, 382/49, 382/54
• US Class Current: 382/303
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

An image morphological processing system is formed by a cascade of a plurality of transformation stages. A pair of handshake data flow control lines couple each pair of adjacent stages. One line carries a first signal indicating when the previous stage has data available at its output and the other line carries a second signal which designates when the subsequent stage is able to receive data from the previous stage. In order that first and second signals can propagate in an orderly manner through a long cascade of stages, each signal is delayed by one cycle of the signal which clocks image data through the cascade. The delayed signal is then coupled to the next stage along the cascade. By controlling the propagation of the control signals to correspond to that of the image data the integrity of the data is maintained. Each stage also includes a circuit which detects when an idempotent transformation is performed by that stage.

Claims

1. An image processing system comprising:

a plurality of processing stages interconnected in a cascade manner, each of the stages for performing a morphological transformation of image data supplied to a data input of that respective stage and applying the results of the transformation to a data output of that respective stage, each stage comprising;

a first data flow control circuit including a first input terminal for receiving a first signal indicating the availability of image data at the data input of the respective stage, means for delaying the first signal by a first given period of time, and means for coupling the delayed first signal to a first output terminal;

a second data flow control circuit including a second input terminal for receiving a second signal indicating the availability of a device connected to the data output of the respective stage to receive the transformed image data from that stage, means for delaying the second signal by a second given period of time, and means for coupling the delayed second signal to a second output terminal; and

means for halting the morphological transformation of image data in response to the absence of at least one of the first and second signals.

2. The image processing system as recited in claim 1 wherein said means responsive to the absence of at least one of the first and second signals halts the morphological transformation substantially immediately upon receipt of the first signal.

3. The image processing system as recited in claim 1 wherein said means responsive to the absence of at least one of the first and second signals halts the morphological transformation after an interval of time substantially equal to the second given period of time from the receipt of the second signal.

4. The image processing system as recited in claim 1 wherein the results of the morphological transformation applied to the data output of the stage are latched upon the halting of the morphological transformation which occurs in response to the receipt of the second signal.

5. The image processing system as recited in claim 1 further comprising means for determining the idempotency of the morphological transformation performed by each stage.

6. The image processing system as recited in claim 1 wherein each stage further comprises as plurality of sections each of which processes a data bit from each pixel in a predefined group of pixels;

means for connecting the plurality of sections in parallel to process a plurality of digital bits representing gray scale image data for each pixel or alternatively connecting the plurality of sections in series to perform of a plurality of morphological transformations on each pixel bit of a binary image; and

means for determining the idempotency of the morphological transformation performed by the stage.

7. The image processing system as recited in claim 6 wherein means of each stage for determining the idempotency of a morphological transformation performed by the stage further comprises means for determining the idempotency of a morphological transformation performed by each section.

14. The image processing system as recited in claim 1 further comprising an interstage coupling means having a first means for connecting the data output of one stage to the data input of a subsequent stage in the cascade, a second means for connecting the first output terminal of the one stage to the first input terminal of the subsequent stage, and a third means for connecting the second input terminal of the one stage to the second output terminal of the subsequent stage.

8. An image processing system comprising:

a plurality of processing stages interconnected in a cascade manner, each of the stages processing image data supplied to a data input of that stage and applying the results of the processing to a data output of that stage, each stage comprising;

a first data flow control circuit including a first input terminal for receiving a first signal indicating the availability of image data at the data input of the stage, means for delaying the first signal by a first given period of time, and means for coupling the delayed first signal to a first output terminal;

a second data flow control circuit including a second input terminal for receiving a second signal indicating the availability of a device connected to the data output of the respective stage to receive the processed image data from that stage, means for delaying the second signal by a second given period of time, and means for coupling the delayed second signal to a second output terminal;

means responsive to the absence of at least one of the first and second signals for controlling the processing of image data; and

each stage, except a last one in the cascade, also comprising means for coupling the first output terminal to the first input terminal of a subsequent stage in the cascade, and for coupling the second input terminal to the second output terminal of the subsequent stage.

9. The image processing system as recited in claim 8 further comprising means for coupling the first output terminal and the second input terminal of a last stage in the cascade to the device connected to the data output of that last stage.

10. The image processing system as recited in claim 8 further comprising means for coupling the first input terminal and the second output terminal of a first stage in the cascade to a device connected to the data input of that first stage.

11. The image processing system as recited in claim 8 wherein said means responsive to the absence of at least one of the first and second signals halts the processing substantially immediately upon receipt of the first signal.

12. The image processing system as recited in claim 8 wherein said means responsive to the absence of at least one of the first and second signals halts the processing after an interval of time substantially equal to the second given period of time from the receipt of the second signal.

13. The image processing system as recited in claim 8 wherein the results of the processing applied to the data output of the stage are latched upon the halting of the morphological transformation which occurs in response to the receipt of the second signal.