Wafer-level burn-in testing of integrated circuits

• US 5,047,711 A
• Filed: 08/23/1989
• Issued: 09/10/1991
• Est. Priority Date: 08/23/1989
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Silicon Connections Corporation
• Inventors: Smith, William H., Chen, Chau-Shiong
• Primary Examiner(s): Wieder, Kenneth A.
• Assistant Examiner(s): Burns, William J.
• Application Number:
  US07/397,768
• Time in Patent Office: 748 Days
• Field of Search: 324/158 P, 324/158 F, 324/158 R, 324/158 D, 324/158 T, 324/158, 324/72.5, 437/8, 357/45
• US Class Current: 324/750.06
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]

Abstract

A wafer containing an array of integrated circuit dice, wherein the dice are separated by scribe lanes in which the wafer may be cut to dice the wafer into individual die, is so constructed as to enable burn-in testing of the integrated circuits while they are still in the wafer. In this wafer, individual integrated circuits of the array include contact pads that extend into the scribe lanes for use during burn-in testing of the integrated circuits while they are contained in the wafer. A system for testing such a wafer includes a testing station for applying and monitoring burn-in test signals for individual integrated circuits; and contact probes for coupling the testing station to the contact pads for a plurality of the individual integrated circuits to enable separate burn-in tests to be conducted simultaneously for a plurality of the individual integrated circuits while they are contained in the wafer. Control means are coupled to the testing means for discontinuing the application of burn-in test signals to a given individual integrated circuit when the monitored test signals for the given integrated circuit indicate that the given integrated circuit has failed the burn-in test.

Claims

1. A wafer containing an array of integrated circuit dice,

wherein the dice are separated by scribe lanes in which the wafer may be cut to dice the wafer into individual die;

and

wherein individual integrated circuits of the array include contact pads that extend from only said individual integrated circuit into the scribe lanes for use during burn-in testing of the integrated circuits while they are contained in the wafer.

2. A wafer according to claim 1, in which the scribe lines are disposed parallel and perpendicular to one another to define an array of rectangular integrated circuits,

wherein a first set of said contact pads extend into said scribe lanes from areas of the integrated circuits near the intersections of the scribe lines for use in providing test stimulus signals during said testing;

and

wherein a second set of said contact pads extend into the scribe lanes from areas of the integrated circuits outside the intersections of the scribe lines for use in providing power to the integrated circuits during said testing.

3. A system for testing a wafer containing an array of integrated circuit dice, wherein the dice are separated by scribe lanes in which the wafer may be cut to dice the wafer into individual die, and wherein individual integrated circuits of the array include contact pads that extend from only said individual integrated circuit into the scribe lanes for use during burn-in testing of the integrated circuits while they are contained in the wafer, the system comprising

testing means for simultaneously applying and separately monitoring burn-in test signals for individual integrated circuits;

and

contact means for coupling said testing means to said contact pads for a plurality of said individual integrated circuits to enable separate burn-in tests to be conducted simultaneously for a plurality of said individual integrated circuits while they are contained in the wafer.

4. A system according to claim 3, further comprising

control means coupled to said testing means for discontinuing the application of burn-in test signals to a given individual integrated circuit when said monitored test signals for said given integrated circuit indicate that said given integrated circuit has failed the burn-in test.

5. A system according to claim 3, for testing a wafer in which the scribe lines are disposed parallel and perpendicular to one another to define an array of rectangular integrated circuits, and in which first sets of said contact pads extend into said scribe lanes from areas of the integrated circuits near the intersections of the scribe lines,

wherein the contact means include clusters of probes for contacting the first sets of contact pads in those areas of the wafer near the intersections of the scribe lines for providing test stimulus signals to the integrated circuits during said testing.

6. A system according to claim 5, for testing a wafer in which second sets of said contact pads extend into said scribe lanes from areas of the integrated circuits outside the intersections of the scribe lines,

wherein the contact means further include probes for contacting the second sets of contact pads in those areas of the wafer outside the intersections of the scribe lines for providing power to the integrated circuits during said testing.

7. A system according to claim 3, further comprising

means for sensing the temperature of the wafer during said testing;

cooling means for receiving the wafer during said testing; and

control means coupled to said sensing means, said cooling means and the testing means for controlling the temperature of wafer during said testing by controlling said cooling means, varying said power, and/or varying said test stimulus signals in accordance with the sensed temperature of the wafer.

8. A method of testing a wafer containing an array of integrated circuit dice, wherein the dice are separated by scribe lanes in which the wafer may be cut to dice the wafer into individual die, and wherein individual integrated circuits of the array include contact pads that extend from only said individual integrated circuit into the scribe lanes for use during burn-in testing of the integrated circuits while they are contained in the wafer, the method comprising the steps of

(a) coupling testing means for applying and monitoring burn-in test signals for individual integrated circuits to said contact pads for a plurality of said individual integrated circuits to enable separate burn-in tests to be conducted simultaneously for said plurality of individual integrated circuits while they are contained in the wafer;

(b) simultaneously applying burn-in test signals to the coupled plurality of individual integrated circuits while they are contained in the wafer; and

(c) separately monitoring burn-in test signals for the coupled individual integrated circuits while they are contained in the wafer.

9. A method according to claim 8 further comprising the step of

(d) discontinuing the application of burn-in test signals to a given individual integrated circuit when said monitored test signals for said given integrated circuit indicate that said given integrated circuit has failed the burn-in test.