Digital error correction system for subranging analog-to-digital converters

• US 5,047,772 A
• Filed: 06/04/1990
• Issued: 09/10/1991
• Est. Priority Date: 06/04/1990
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Ribner, David B.
• Primary Examiner(s): Scott, J. R.
• Assistant Examiner(s): Logan, Sharon D.
• Application Number:
  US07/533,263
• Time in Patent Office: 463 Days
• Field of Search: 341/161, 341/120, 341/118, 341/156, 341/162, 341/155
• US Class Current: 341/156
• CPC Class Codes: H03M 1/1042 the look-up table containing corrected values for replacing the original digital values H03M1/1052 takes precedence
• CPC Class Codes: H03M 1/1061 using digitally programmable trimming circuits
• CPC Class Codes: H03M 1/167 all stages comprising simultaneous converters H03M1/165 takes precedence

Abstract

A general architecture to correct conversion errors of a multi-stage, pipelined subranging analog-to-digital (A/D) converter includes cascaded stages, each stage generating a binary conversion signal representing the nearest quantized level below that of the analog input signal and a residual analog signal applied to the next conversion stage. The binary conversion signal from each stage addresses individual or common look-up tables providing a compensated binary signal selected to compensate for nonidealities of the A/D converter components. The compensated binary signals from the look-up tables provide a corrected output signal when summed together. A simple method of calibration for the A/D converter makes use of a least-mean-squared adaptation algorithm. The A/D converter accommodates practical circuit nonidealities such as component mismatching, gain error and voltage offsets, and handles high levels of amplifier nonlinearity. The architecture is applicable to any subranging converter with arbitrary numbers of stages and bits per stage.

Claims

1. A multi-stage pipelined subranging analog-to-digital converter, comprising:

a plurality of cascade-coupled conversion stages, each of said stages including first means responsive to an analog input signal for generating a binary conversion signal corresponding to the nearest guantized level below that of the analog input signal, second means responsive to said binary conversion signal for generating a quantized analog signal corresponding tot he nearest quantized level below that of the analog input signal, third means for subtracting the quantized analog signal from the analog input signal to generate a residual analog signal for application to the next conversion stage, and a look-up table for generating a compensated binary signal selected by said binary conversion signal, said look-up table being coupled to the output of said first means by circuit means in the final stage of said converter and by delay means introducing incrementally larger delays in each successive earlier stage, respectively; and

means for combining said compensated binary signals from said look-up tables into a binary output signal.

2. The analog-to-digital converter of claim 1 wherein each of said look-up tables comprises memory means for storing compensated binary signals adjusted to compensate for nonidealities in components of said conversion stages.

3. The analog-to-digital converter of claim 1 including:

a separate interstage amplifier located, respectively, between each set of successive conversion stages, respectively, the gain of each of said amplifiers being less than 2ⁿⁱ where n_i is the number of bits in the binary conversion signal of each stage preceding a respective one of said amplifiers.

4. The analog-to-digital converter of claim 3 wherein, in each conversion stage, the look-up table includes a number of binary address inputs equal to the number n_i of bits of said first means in said each conversion stage and contains 2ⁿⁱ coefficients.

5. A multi-stage, pipelined subranging analog-to-digital converter, comprising:

a plurality of cascade-coupled conversion stages, each of said stages including first means responsive to an analog input signal for generating a binary conversion signal corresponding to the nearest quantized level below that of the analog input signal, second means responsive to said binary conversion signal for generating a quantized analog signal corresponding to the nearest quantized level below that of the analog input signal, third means for subtracting the quantized analog signal from the analog input signal to generate a residual analog signal for application to the next conversion stage, and a look-up table for generating a compensated binary signal selected by said binary conversion signal, said look-up table including a number of binary address inputs equal to the number n_i of bits of said first means in said each conversion stage, said binary word size of each coefficient in said look-up table being greater than the total number of bits n_i of said first means in said each conversion stage to facilitate correction and calibration of said analog-to-digital converter;

a separate interstage amplifier located, respectively, between each set of successive conversion stages, respectively, the gain of each of said amplifiers being less than 2ⁿⁱ where n_i is the number of bits in the binary conversion signal of each stage preceding a respective one of said amplifiers; and

means for combining said compensated binary signals from said look-up tables into a binary output signal.

6. A multi-stage, pipelined subranging analog-to-digital converter comprising:

a plurality of cascade-coupled conversion stages, each of said stages including first means responsive to an analog input signal for generating a binary conversion signal corresponding to the nearest quantized level below that of the analog input signal, second means responsive to said binary conversion signal for generating a quantized analog signal corresponding to the nearest quantized level below that of the analog input signal, and third means for subtracting the quantized analog signal from the analog input signal to generate a residual analog signal for application to the next conversion stage;

a common look-up table for at least a predetermined number of most significant bit conversion stages for generating a compensated binary signal selected by said binary conversion signals of said most significant bit stages;

a separate look-up table for each respective one of the conversion stages not included within said predetermined number, for generating a compensated binary signal selected by said binary conversion signal of each respective one of said conversion stages not included within said predetermined number; and

means for combining said compensated binary signals from said common look-up table and said separate look-up tables into a binary output signal.

7. The multi-stage, pipelined subranging analog-to-digital converter of claim 6 including;

a separate interstage amplifier located, respectively, between each set of successive conversion stages, respectively, the gain of each of said amplifiers being less than 2ⁿⁱ where n_i is the number of bits in the binary conversion signal of each stage preceding a respective one of said amplifiers.

8. A multi-stage, pipelined subranging analog-to-digital converter, comprising:

a plurality of cascade-coupled conversion stages, each of said stages including an analog-to-digital converter for converting an analog input signal into a binary conversion signal corresponding to the nearest quantized level below that of the analog input signal, a digital-to-analog converter for converting said binary conversion signal into a quantized analog signal corresponding to the nearest quantized level below that of the analog input signal, summation means for subtracting the quantized analog signal from the analog input signal to generate a residual analog signal for application to the next conversion stage, an interstage amplifier coupling said each of said stages to the next successive conversion stage, the gain of said amplifier being less than 2ⁿⁱ where n.sub. is the number of bits in the binary conversion signal of said each of said stages, and a look-up table for generating a compensated binary signal selected by said binary conversion signal, said look-up table having n_i binary address inputs and 2ⁿⁱ coefficients and

wherein, in said each conversion stage, binary word size of each coefficient in said look-up table is greater than the total number of bits n_i of the analog-to-digital converter therein to facilitate correction and calibration of said multi-stage, pipelined subranging analog-to-digital converter; and

means for combining said compensated binary signals from the look-up tables into a binary output signal.

9. A multi-stage, pipelined subranging analog-to-digital converter comprising:

a plurality of cascade-coupled conversion stages, each of said stages including an analog-to-digital converter for converting an analog input signal into a binary conversion signal corresponding to the nearest quantized level below that of the analog input signal, a digital-to-analog converter for converting said binary conversion signal into a quantized analog signal corresponding to the nearest quantized level below that of the analog input signal, summation means for subtracting the quantized analog signal from the analog input signal to generate a residual analog signal for application to the next conversion stage, an interstage amplifier coupling said each of said stages to the next successive conversion stage, the gain of said amplifier being less than 2ⁿⁱ where n_i is the number of bits in the binary conversion signal of said each of said stages;

a plurality of look-up tables for generating a compensated binary signal selected by said binary conversion signal, a first of said look-up tables being coupled to a plurality of said stages producing the most significant bits, and at least a separate look-up table being coupled to the stage producing the least significant bit; and

means for combining said compensated binary signals from the look-up tables into a binary output signal.

10. The multi-stage, pipelined subranging analog-to-digital converter of claim 9 wherein, in said each conversion stage, the look-up table coupled thereto comprises memory means for storing compensated binary output signals selected to compensate for nonidealities in components of said each conversion stage.

11. The multi-stage, pipelined subranging analog-to-digital converter of claim 9 wherein, in said each conversion stage, binary word size of each coefficient in said look-up table is greater than the total number of bits of the analog-to-digital converters coupled thereto to facilitate correction and calibration of said multi-stage, pipelined subranging analog-to-digital converter.

12. The multi-stage, pipelined subranging analog-to-digital converter of claim 9 including at least a third look-up table coupled to the stages subsequent to said plurality of said stages producing the most significant bits.

13. A digital calibration system for a multi-stage, pipelined subranging analog-to-digital converter, said converter including a plurality of cascade-coupled conversion stages, each of said stages including an analog-to-digital conversion signal corresponding to the nearest quantized level below that of the analog input signal, a digital-to-analog converter for converting said binary conversion signal into a quantized analog signal corresponding to the nearest quantized level below that of the analog input signal, summation means for subtracting the quantized analog signal from the analog input signal to generate a residual analog signal for application to the next conversion stage, and a look-up table for generating a compensated binary signal selected by said binary conversion signal, said converter further including means for combining the compensated binary signals from the look-up tables in each of said stages into a binary output signal, said digital calibration system comprising:

a plurality of calibration look-up tables corresponding, respectively, to the look-up tables of the analog-to-digital converter conversion stages;

means for applying an analog input signal to the multi-stage analog-to-digital converter;

means for applying the binary conversion signals from the analog-to-digital converters of said conversion stages to said calibration look-up tables;

means for combining the compensated binary signals from said calibration look-up tables into a binary calibration signal;

means for comparing the binary calibration signal with another binary signal corresponding to the analog input signal applied to the multi-stage analog-to-digital converter, to produce an error signal; and

means responsive to the error signal for correcting the compensated binary signals stored in said calibration look-up tables.

14. The digital calibration system of claim 13 including means for writing memory data from the calibration look-up tables into the look-up tables of the multi-stage analog-to-digital converter after calibration is completed.

15. The digital calibration system of claim 13 including:

a random sequence generator for generating, as said another binary signal, a binary signal which is compared with the binary calibration signal; and

means for converting said random binary signal into said analog input signal applied to the multi-stage analog-to-digital converter.

16. The digital calibration system of claim 13 including:

a random signal generator for generating a random analog signal for application to the multi-stage analog-to-digital converter as said analog input signal; and

means for converting said random analog signal into said another binary signal for comparison with said binary calibration signal.

17. The digital calibration system of claim 13 wherein said means responsive to the error signal comprises a processor further responsive to the binary conversion signal from each stage of the multi-stage analog-to-digital converter for correcting the compensated binary signals stored in said calibration look-up tables and storing the corrected compensated binary signals in said look-up tables of the multi-stage analog-to-digital converter.

18. A digital calibration system for a multi-stage, pipelined subranging analog-to-digital converter, said converter including a plurality of cascade-coupled conversion stages, each of said stages including an analog-to-digital converter for converting an analog input signal into a binary conversion signal corresponding to the nearest quantized level below that of the analog input signal, a digital-to-analog converter for converting said binary conversion signal into a quantized analog signal corresponding to the nearest quantized level below that of the analog input signal, and summation means for subtracting the quantized analog signal from the analog input signal to generate a residual analog signal for application to the next conversion stage, said converter further including a plurality of look-up tables for generating a compensated binary signal selected by those of the binary conversion signals respectively supplied thereto, and means for combining the compensated binary signals from the look-up tables into a binary output signal, said digital calibration system comprising:

a plurality of calibration look-up tables corresponding, respectively, to the look-up tables of the analog-to-digital converter;

means for applying an analog input signal to the multi-stage analog-to-digital converter;

means for applying the binary conversion signals from the analog-to-digital converters of said conversion stages to said calibration look-up tables;

means for combining the compensated binary signals from said calibration look-up tables into a binary calibration signal;

means for comparing the binary calibration signal with another binary signal corresponding to the analog input signal applied to the multi-stage analog-to-digital converter, to produce an error signal; and

means responsive to the error signal for correcting the compensated binary signals stored in said calibration look-up tables.

19. The digital calibration system of claim 18 including means for writing memory data from the calibration look-up tables into the look-up tables of the multi-stage analog-to-digital converter after calibration is completed.

20. The digital calibration system of claim 18 including

a random sequence generator for generating, as said another binary signal, a binary signal which is compared with the binary calibration signal;

and

means for converting said random binary signal into said analog input signal applied to the multi-stage analog-to-digital converter.

21. The digital calibration system of claim 18 including:

a random signal generator for generating a random analog signal for application to the multi-stage analog-to-digital converter as said analog input signal; and

means for converting said random analog signal into said another binary signal for comparison with said binary calibration signal.

22. The digital calibration system of claim 18 wherein said means responsive to the error signal comprises a processor further responsive to the binary conversion signal from the multi-stage analog-to-digital converter for correcting the compensated binary signals stored in said calibration look-up tables and storing the corrected compensated binary signals in said look-up tables of the multi-stage analog-to-digital converter.