Semiconductor memory device having a trench-stacked capacitor

• US 5,047,815 A
• Filed: 08/14/1989
• Issued: 09/10/1991
• Est. Priority Date: 08/18/1988
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Matsuyama, Kazuhiro, Yasui, Takatoshi, Yasuhira, Mitsuo, Iwata, Hideyuki, Fukumoto, Masanori
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Bowers, Courtney A.
• Application Number:
  US07/394,123
• Time in Patent Office: 757 Days
• Field of Search: 357/23.6, 357/55, 357/51, 357/54, 357/23.6 G
• US Class Current: 257/303
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

A semiconductor memory device includes a capacitor and an insulating separation area in a trench formed around a switching transistor, with a storage electrode of the capacitor being sandwiched between an upper and a lower cell plate electrode to reduce leakage current due to the parasitic MOS transistor effect in the trench sidewall along the channel in the switching transistor and leakage current due to the gate-controlled diode effect in the trench sidewall. Also, a method is disclosed for manufacturing such semiconductor memory device.

Claims

1. A semiconductor memory device comprising:

a semiconductor substrate including a plurality of trenches formed therein;

an insulating film formed on a bottom and a sidewall of at least one of said trenches;

a first cell plate electrode provided in said one of said trenches;

a first capacitor insulating film formed on said first cell plate electrode;

a storage electrode formed on said first capacitor insulating film, said storage electrode being connected with a source area of a switching transistor of a unit cell of said memory device which is separated electrically from an adjacent unit cell of said memory device;

a second capacitor insulating film formed on said storage electrode; and

a second cell plate electrode formed on said second capacitor insulating film, said first and second cell plate electrodes being connected with each other and supplied with a given bias voltage from an external circuit;

wherein said insulating film formed on said at least one of said trenches and said first and second capacitor insulating films provide an element separating area whereby the unit cell disposed in said one of said trenches is electrically isolated from an adjacent unit cell disposed in an adjacent one of said trenches, the switching transistor being formed in an island surrounded by said at least one of said trenches.

2. A semiconductor memory device according to claim 1, wherein the first and second cell plate electrodes are made of a semiconductor layer of the same conductivity type as that of the semiconductor substrate and are connected with the semiconductor substrate at said bottom of said one of said trenches.

3. A semiconductor memory device according to claim 1, wherein the first and second cell plate electrodes are made of a semiconductor layer opposite in conductivity type to that of the semiconductor substrate, and an impurity diffusion layer of the same conductivity type as that of the semiconductor layer of the first and second cell plate electrodes is provided on the semiconductor substrate at a position where said insulating film is removed from said bottom of said one of said trenches, the first and second cell plate electrodes being connected with the impurity diffusion layer at the bottom of said one of said trenches and being supplied with said given bias voltage from said external circuit through the impurity diffusion layer.

4. A semiconductor memory device comprising:

a semiconductor substrate having a plurality of trenches formed therein;

an insulating film formed on a bottom and a sidewall of at least one of said trenches;

a first cell plate electrode provided in said one of said trenches;

a first capacitor insulating film formed on said first cell plate electrode;

a storage electrode formed on said first capacitor insulating film, said storage electrode being connected with a source area of a switching transistor of a unit cell of said memory device;

a second capacitor insulating film formed on said storage electrode; and

a second cell plate electrode formed on said second capacitor insulating film, said first and second cell plate electrodes being connected with each other and supplied with a given bias voltage from an external circuit.