Amorphous-silicon thin film transistor array substrate

• US 5,047,819 A
• Filed: 07/12/1990
• Issued: 09/10/1991
• Est. Priority Date: 02/26/1988
• Status: Expired due to Term

• Current Assignee: Seiko Precision Incorporated (Seiko Group)
• Original Assignee: Seikosha Co., Ltd.
• Inventors: Watanabe, Yoshiaki, Tanaka, Sakae
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US07/551,688
• Time in Patent Office: 425 Days
• Field of Search: 357/23.7, 357/2.4, 357/45, 357/71, 350/336
• US Class Current: 257/350
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 23/4825 for devices consisting of semiconductor layers on insulating or semi-insulating substrates, e.g. silicon on sapphire devices, i.e. SOS
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A reverse staggered amorphous silicon thin film transistor array substrate includes an array of amorphous silicon thin film transistors, gate wiring interconnecting the gate electrodes of the amorphous silicon thin film transistors, and source wirings. The transistor array is provided on a thin film transistor array substrate. A protective insulation layer and an amorphous silicon layer having a greater width than the source wiring are provided under the source wiring.

Claims

1. In a reverse staggered amorphous silicon thin film transistor array substrate including an array of amorphous silicon thin film transistors having source and gate electrodes, gate wirings connected to the gate electrodes of said amorphous silicon thin film transistors, a gate insulating layer deposited on said gate wirings and gate electrodes, source wirings extending in a given direction, having a given width and arranged to cross said gate wirings to define a plurality of cross overs, an amorphous silicon layer deposited on said gate insulating layer at said cross overs, a protective insulation layer deposited on said amorphous silicon layer at said cross overs and having a greater width than said given width, said source wiring being deposited on said protective insulation layer at said cross overs, said source wirings being connected to the source electrodes of said amorphous silicon thin film transistors at locations spaced from said cross overs, said source wiring being of a different material than said source electrodes, said substrate comprising an amorphous-silicon thin film transistor array substrate, the improvement wherein said amorphous silicon layer is deposited on said gate insulating layer at said locations, said protective insulation layer is deposited on said amorphous silicon layer at said locations, said source electrode is formed on said protective insulation layer at said locations, said source wiring is formed on said source electrode at said locations, whereby said protective insulation layer and amorphous silicon layer extend from said cross overs in the direction of said source wiring at least as far as said source electrodes, whereby level changes in said source wiring adjacent said cross overs are minimized.

2. The amorphous silicon thin film transistor of claim 1 wherein said protective insulation layer extends substantially continuously with said source wiring.

3. In a reverse staggered amorphous silicon thin film transistor array substrate including an array of amorphous silicon thin film transistors having gate electrodes and source electrodes, gate wirings connected to the gate electrodes of said amorphous silicon thin film transistors, a gate insulating layer deposited on said gate wirings and gate electrodes, source wirings extending in a given direction having a given width and arranged to cross said gate wirings to define a plurality of cross overs, an amorphous silicon layer deposited on said gate insulating layer at said cross overs, a protective insulation layer deposited on said amorphous silicon layer at said cross overs and having a greater width than said given width, said source wiring being deposited on said protective insulation layer at said cross overs, said source wirings being connected to the source electrodes of said amorphous silicon thin film transistors at locations spaced from said cross overs, said source wiring being of a different material than said source electrodes, said substrate comprising an amorphous-silicon thin film transistor array substrate, the improvement wherein said amorphous silicon layer is deposited on said gate insulating layer at said locations, said protective insulation layer is deposited on said amorphous silicon layer at said locations, said source electrode is formed on said protective insulation layer at said locations, and said source wiring is formed on said source electrode at said locations, said source wiring having a given level and being deposited primarily solely on said protective insulation layer, said protective insulation layer and amorphous silicon layer extending in the direction of said source wiring a sufficient distance that the level of said source wiring does not change substantially adjacent said transistors.

4. In a reverse staggered amorphous silicon thin film transistor array substrate including an array of amorphous silicon thin film transistors having gate electrodes and source electrodes, gate wirings connected to the gate electrodes of said amorphous silicon thin film transistors, a gate insulating layer deposited on said gate wirings and gate electrodes, source wirings extending in a gate direction having a given width and arranged to cross said gate wirings to define a plurality of cross overs, an amorphous silicon layer deposited on said gate insulating layer at said cross overs, a protective insulation layer deposited on said amorphous silicon layer at said cross overs and having a greater width than said given width, said source wiring being deposited on said protective insulation layer at said cross overs, said source wirings being connected to the source electrodes of said amorphous silicon thin film transistors at locations spaced from said cross overs, said source wiring being of a different material than said source electrodes, said substrate comprising an amorphous silicon thing film transistor array substrate, the improvement wherein said amorphous silicon layer is deposited on said gate insulating layer at said locations, said protective insulation layer is deposited on said amorphous silicon layer at said locations, said source electrode is formed on said protective insulation layer at said locations, and said source wiring is formed on said source electrodes at said locations, whereby said protective insulation layer has at least one stepped edge, said protective insulation layer and amorphous silicon layer extending substantially continuously with said source wiring, said source wiring being formed primarily on said protective insulation layer so as to avoid crossing over the stepped edge of said protective insulation layer.