Standard cell LSI layout method

• US 5,047,949 A
• Filed: 06/06/1990
• Issued: 09/10/1991
• Est. Priority Date: 06/10/1987
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Yamaguchi, Ryuichi, Yamamoto, Atsushi
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): TRANS, VINCENT N
• Application Number:
  US07/534,358
• Time in Patent Office: 461 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/119
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits

Abstract

In a standard cell LSI including functional circuits formed by placing a group of cell rows consisting of standard cells selected from a group of standard cells and by routing the standard cells, a standard cell LSI layout method including the steps of comparing the routing density in routing areas located between the cell rows and bending the cell rows by shifting one or more of the standard cells in a direction of a more dispersed routing area from a more congested routing area. The cell rows are bent at a point between each high congested area of the routing area which encloses the cell rows depending on the routing density. A link cell may be provided for linking power and ground pins of the standard cells which have been shifted in position and which compose the bent cell rows. The link cell may be stored in a library in a system of composing the cell rows by storing the standard cells in a library and referring to the standard cells from the library in defining a standard cell LSI layout.

Claims

1. In a standard cell LSI comprising functional circuits formed by placing a plurality of cell rows consisting of a plurality of standard cells and by routing said standard cells, a standard cell LSI layout method comprising the steps of:

deciding a global routing path which connects signal pins of said standard cells; and

determining the routing density from said global routing path in routing channels between cell rows; and

bending said cell rows in a zigzag lien by shifting one or more of said standard cells in a direction of a more dispersed routing area from a more congested routing area in order to avoid congested routing area between said cell rows; and

shifting at least one cell row in order to eliminate wiring area containing no wiring between said cell rows, which is produced as a result of bending of cell rows; and

connecting said signal pins of said standard cells by generating routing patterns.

2. A standard cell LSI layout method according to claim 1, further comprising the step of providing at least one link cell for linking power and ground pins of said standard cells which have been shifted in position and which compose the cell rows which have been bent.