Linear address conversion

• US 5,047,958 A
• Filed: 06/15/1989
• Issued: 09/10/1991
• Est. Priority Date: 06/15/1989
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Comins, Todd R., Engelse, Willem A. H.
• Primary Examiner(s): Clark, David L.
• Assistant Examiner(s): Bayerl, Raymond J.
• Application Number:
  US07/366,859
• Time in Patent Office: 817 Days
• Field of Search: 364/521, 364/518, 340/798, 340/799, 340/802, 340/750, 340/721
• US Class Current: 345/548
• CPC Class Codes: G09G 3/003 to produce spatial visual effects
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A graphics subsystem (10) employs an image memory (12) that includes an on-screen part (44) and an off-screen part (46). The locations of the on-screen memory (44) are continually scanned to provide data to be displayed on a display device (16). The off-screen part (46) stores data that represent image segments that have been occluded by windowing. To transfer data between the on-screen part (44) and the off-screen part (46), an address generator (24) generates a sequence of two-dimensional addresses representing the two-dimensional positions of the pixels whose data are to be transferred. These addresses are converted to one-dimensional addresses by a simple circuit consisting of multiplexers (26 and 28), adders (30 and 32) and a multiplier (34).

Claims

1. A display system comprising:

A. an on-screen memory containing a two-dimensional array of memory locations for storing image data representing the values of image pixels;

B. display means for repetitively scanning the contents of the on-screen memory and generating a visual display of the image that they represent;

C. an off-screen memory containing a two-dimensional array of memory locations for storing image data representing the values of image pixels;

D. an address circuit comprising;

i. means for receiving input signals that represent (a) as an off-screen-segment offset value, the position of an off-screen segment of the off-screen memory, the off-screen segment having a beginning location, (b) a location in a corresponding on-screen segment of the on-screen memory as x and y components of the address of the location, (c) the width of the on-screen segment, (d) an on-screen-segment offset value, and (e) the width of the off-screen memory;

ii. a first multiplexer, including two input ports, for receiving at one input port the signals representing the width of the on-screen segment, for receiving at its other input port the signals representing the width of the off-screen memory, and for selectively forwarding as a first multiplexer output the signals received at one of its input ports;

iii. a multiplier for multiplying the y component of the width that the first multiplexer output represents and generating as the product signal a signal representative of the resultant product;

iv. a second multiplexer, including two input ports, for receiving at one input port the signals representing the off-screen-segment offset value, for receiving at its other input port signals representing the on-screen-segment offset values, and for selectively forwarding as a second multiplexer output the signals received at one of its input ports;

v. addition means for adding the product, the x component, and the offset value that the second multiplexer output represents and generating as the address signal a signal representing the resultant sum; and

vi. means for applying the address signal to the off-screen memory and to the on-screen memory; and

E. access means for reading from and writing to the on-screen-memory and off-screen-memory locations that the address signal represents.

2. A display system as defined in claim 1 wherein the address circuit further includes an address generator for generating and applying to the means for receiving input signals the input signals that represent a location in an on-screen segment of the on-screen memory as x and y components of the address thereof.

3. A display system comprising:

A. an on-screen memory containing a two-dimensional array of memory locations for storing image data representing the values of image pixels;

B. display means for repetitively scanning the contents of the on-screen memory and generating a visual display of the image that they represent;

C. an off-screen memory containing a two-dimensional array of memory locations for storing image data representing the values of image pixels;

D. an address circuit comprising;

i. means for receiving input signals that represent (a) as an off-screen-segment offset value, the position of an off-screen segment of the off-screen memory, the off-screen segment having a beginning location, (b) a location in a corresponding on-screen segment of the on-screen memory as x and y components of the address of the location, (c) the width of the on-screen segment, (d) an on-screen segment offset value, and (e) the width of the off-screen memory;

ii. a first multiplexer, including two input ports, for receiving at one input port the signals representing the width of the on-screen segment, for receiving at its other input port the signals representing the width of the off-screen memory, and for selectively forwarding as a first multiplexer output the signals received at one of its input ports;

iii. a multiplier for multiplying the y component by the width that the first multiplexer outputs represents and generating as the product signal a signal representative of the resultant product;

iv. a second multiplexer, including two input ports, for receiving at one input port the signals representing the off-screen-segment offset value, for receiving at its other input port signals representing the on-screen-segment offset value, and for selectively forwarding as a second multiplexer output the signals received at one of its input ports;

v. a first adder for adding the x component to the offset value that the second multiplexer output represents and generating a signal representing a first sum;

vi. a second adder for adding the first sum to the product and generating as the address signal a signal representing the resultant sum; and

vii. means for applying the address signal to the off-screen memory and to the on-screen memory; and

E. access means for reading from and writing to the on-screen-memory and off-screen-memory locations that the address signal represents.

4. A display system comprising:

A. an on-screen memory containing a two-dimensional array of memory locations for storing image data representing the values of image pixels;

B. display means for repetitively scanning the contents of the on-screen memory and generating a visual display of the image that they represent;

C. an off-screen memory containing a two-dimensional array of memory locations for storing image data representing the values of image pixels;

D. an address circuit comprising;

i. an address generator for generating on-screen-address signals representing a location in an on-screen segment of the on-screen memory as x and y components of the address of the location;

ii. means for receiving as input signals the on-screen-address signals and signals that represent (a) as an off-screen-segment offset value, the position of a corresponding off-screen segment of the off-screen memory, the off-screen segment having a beginning location, (b) the width of the on-screen segment, (c) an on-screen segment offset value, and (d) the width of the off-screen memory;

iii. a first multiplexer, including two input ports, for receiving at one input port the signals representing the width of the on-screen segment, for receiving at its other input port the signals representing the width of the off-screen memory, and for selectively forwarding as a first multiplexer output the signals received at one of its input ports;

iv. a multiplier for multiplying the y component by the width that the first multiplexer output represents and generating as the product signal a signal representative of the resultant product;

v. a second multiplexer, including two input ports, for receiving at one input port the signals representing the off-screen-segment offset value, for receiving at its other input port signals representing the on-screen-segment offset value, and for selectively forwarding as a second multiplexer output the signals received at one of its input ports;

vi. a first adder for adding the x component to the offset value that the second multiplexer output represents and generating a signal representing a first sum;

vii. a second adder for adding the first sum to the product and generating as the address signal a signal representing the resultant sum; and

viii. means for applying the address signal to the off-screen memory and to the on-screen memory;

E. access means for reading from and writing to the on-screen-memory and off-screen-memory locations that the address signal represents.

5. An address circuit for use in a display system that includes an on-screen memory containing a two-dimensional array of memory locations for storing image data representing the values of image pixels, display means for repetitively scanning the contents of the on-screen memory and generating a visual display of the image that they represent, an off-screen memory containing a two-dimensional array of memory locations for storing image data representing the values of image pixels, and access means for performing at least one of (i) reading from and (ii) writing to an off-screen-memory location represented by an address signal applied to the off-screen memory, the address circuit comprising:

A. means for receiving input signals that represent (i) as an off-screen-segment offset value, the position of an off-screen segment of the off-screen memory, the off-screen segment having a beginning location, (ii) a location in a corresponding on-screen segment of the on-screen memory as x and y components of the address of the location, (iii) the width of the on-screen segment, (iv) an on-screen-segment offset value, and (v) the width of the off-screen memory;

B. a first multiplexer, including two input ports, for receiving at one input port the signals representing the width of the on-screen segment, for receiving at its other input port the signals representing the width of the off-screen memory, and for selectively forwarding as a first multiplexer output the signals received at one of its input ports;

C. a multiplier for multiplying the y component by the width that the first multiplexer output represents and generating as the product signal a signal representative of the resultant product;

D. a second multiplexer, including two input ports, for receiving at one input port the signals representing the off-screen-segment offset value, for receiving at its other input port signals representing the on-screen-segment offset value, and for selectively forwarding as a second multiplexer output the signals received at one of its input ports;

E. addition means for adding the product, the x component, and the offset value that the second multiplexer output represents and generating as the address signal a signal representing the resultant sum; and

F. means for applying the address signal to the off-screen memory and to the on-screen memory.

6. An address circuit as defined in claim 5 further including an address generator for generating and applying to the means for receiving input signals the input signals that represent a location in an on-screen segment of the on-screen memory as x and y components of the address thereof.

7. An address circuit for use in a display system that includes an on-screen memory containing a two-dimensional array of memory locations for storing image data representing the values of image pixels, display means for repetitively scanning the contents of the on-screen memory and generating a visual display of the image that they represent, an off-screen memory containing a two-dimensional array of memory locations for storing image data representing the values of image pixels, and access means for performing at least one of (i) reading from and (ii) writing to an off-screen-memory location represented by an address signal applied to the off-screen memory, the address circuit comprising:

A. means for receiving input signals that represent (i) as an off-screen-segment offset value, the position of an off-screen segment of the off-screen memory, the off-screen segment having a beginning location (ii) a location in a corresponding on-screen segment of the on-screen memory as x and y components of the address of the location, (iii) the width of the on-screen segment, (iv) an on-screen segment offset value, and (v) the width of the off-screen memory;

B. a first multiplexer, including two input ports, for receiving at one input port the signals representing the width of the on-screen segment, for receiving at its other input port the signals representing the width of the off-screen memory, and for selectively forwarding as a first multiplexer output the signals received at one of its input ports;

C. a multiplier for multiplying the y component by the width that the first multiplexer output represents and generating as the product signal a signal representative of the resultant product;

D. a second multiplexer, including two input ports, for receiving at one input port the signals representing the off-screen-segment offset value, for receiving at its other input port signals representing the on-screen-segment offset value, and for selectively forwarding as a second multiplexer output the signals received at one of its input ports;

E. a first adder for adding the x component to the offset value that the second multiplexer output represents and generating a signal representing a first sum;

F. a second adder for adding the first sum to the product and generating as the address signal a signal representing the resultant sum; and

G. means for applying the address signal to the off-screen memory and to the on-screen memory.

8. An address circuit for use in a display system that includes an on-screen memory containing a two-dimensional array of memory locations for storing image data representing the values of image pixels, display means for repetitively scanning the contents of the on-screen memory and generating a visual display of the image that they represent, an off-screen memory containing a two-dimensional array of memory locations for storing image data representing the values of image pixels, and access means for performing at least one of (i) reading from and (ii) writing to an off-screen-memory location represented by an address signal applied to the off-screen memory, the address circuit comprising:

A. an address generator for generating on-screen-address signals representing a location in an on-screen segment of the on-screen memory as x and y components of the address of the location;

B. means for receiving as input signals the on-screen address signals and signals that represent (i) as an off-screen-segment offset value, the position of the corresponding off-screen segment of the off-screen memory, the off-screen segment having a beginning location, (ii) the width of the on-screen segment, (iii) an on-screen segment offset value, and (iv) the width of the off-screen memory;

C. a first multiplexer, including two input ports, for receiving at one input port the signals representing the width of the on-screen segment, for receiving at its other input port the signals representing the width of the off-screen memory, and for selectively forwarding as a first multiplexer output the signals received at one of its input ports;

D. a multiplier for multiplying the y component by the width that the first multiplexer output represents and generating as the product signal a signal representative of the resultant product;

E. a second multiplexer, including two input ports, for receiving at one input port the signals representing the off-screen-segment offset value, for receiving at its other input port signals representing the on-screen-segment offset value, and for selectively forwarding as a second multiplexer output the signals received at one of its input ports;

F. a first adder for adding the x component to the offset value that the second multiplexer output represents and generating a signal representing a first sum;

G. a second adder for adding the first sum to the product and generating as the address signal a signal representing the resultant sum; and

H. means for applying the address signal to the off-screen memory and to the on-screen memory.