High density SRAM circuit with ratio independent memory cells

• US 5,047,979 A
• Filed: 06/15/1990
• Issued: 09/10/1991
• Est. Priority Date: 06/15/1990
• Status: Expired due to Term

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Leung, Wingyu
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/538,998
• Time in Patent Office: 452 Days
• Field of Search: 365/154, 365/189.01, 365/182
• US Class Current: 365/154
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits

Abstract

Briefly, a high density, static, random access memory (SRAM) circuit with ratio independent memory cells employs a number (plurality) of (4T-2R) or (6T) type SRAM cells and a regenerative sense amplifier. Each of the SRAM cells of the present invention differs from corresponding, prior art type SRAM cells in that the SRAM cells of the present invention each include transistors of similar size (channel width).

Claims

1. A static, random access memory circuit comprising in combination:

a first bit line (430);

a second bit line (440);

a memory cell (400) including,

a word line (432),

a first resistor (420),

a second resistor (422),

a first transistor (410) having a gate connected to said memory cell word line (432) and a channel having a first end connected to said first bit line (430) and a second end coupled by said memory cell first resistor (420) to (434) a power supply potential,

a second transistor (416) having a gate connected to said memory cell word line (432) and a channel having a first end connected to said second bit line (430) and a second end coupled by said memory cell second resistor (422) to (434) the power supply potential,

a third transistor (412) having a gate connected to said memory cell second transistor (416) channel second end and a channel connected between said memory cell first transistor (410) channel second end and a circuit ground potential, and

a fourth transistor (414) having a gate connected to said memory cell first transistor (410) channel second end and a channel connected between said memory cell second transistor (416) channel second end and the circuit ground potential; and

a regenerative sense amplifier (504) including,

a regenerative sense amplifier first line (534),

a regenerative sense amplifier second line (536),

a first transistor (512) having a gate connected to said second bit line (440) and a channel connected between said first bit line (430) and said regenerative sense amplifier second line (536),

a second transistor (514) having a gate connected to said first bit line (430) and a channel connected between said second bit line (440) and said regenerative sense amplifier second line (536),

a third transistor (520) having a gate connected to said second bit line (440) and a channel connected between said regenerative sense amplifier first line (534) and said first bit line (430), and

a fourth transistor (522) having a gate connected to said first bit line (430) and a channel connected between said regenerative sense amplifier first line (534) and said second bit line (440).

2. A static, random access memory circuit as recited in claim 1 wherein said regenerative sense amplifier (504) further includes,

a first sense amplifier selecting line (566),

a second sense amplifier selecting line (576),

a fifth transistor (560) having a gate connected to said regenerative sense amplifier first sense amplifier selecting line (566) and a channel connected between said regenerative sense amplifier first line (534) and the power supply potential (564) and

a sixth transistor (562) having a gate connected to said regenerative sense amplifier second sense amplifier selecting line (576) and a channel connected between said regenerative sense amplifier second line (536) and the circuit ground potential.

3. A static, random access memory circuit as recited in claim 2 wherein said memory cell first (410), second (416), third (412), and fourth (414) transistors each have a channel width which is within fifty percent of a predetermined width.

4. A static, random access memory circuit as recited in claim 1 ,wherein said memory cell first (410), second (416), third (412), and fourth (414) transistors each have a channel width which is within fifty percent of a predetermined width.

5. A static, random access memory circuit as recited in claim 1 further comprising a bit lines equalization circuit including,

a equalization control line (592), and

a transistor (590) having a gate connected to said bit lines equalization circuit equalization control line (592) and a channel having a first end connected to said first bit line (430) and a second end connected to said second bit line (440).

6. A static, random access memory circuit comprising in combination:

a first bit line (730);

a second bit line (740);

a memory cell (700) including,

a word line (732),

a first resistor (720),

a second resistor (722),

a first transistor (710) having a gate connected to said memory cell word line (732) and a channel having a first end connected to said first bit line (730) and a second end,

a second transistor (716) having a gate connected to said memory cell word line (732) and a channel having a first end connected to said second bit line (730) and a second end,

a third transistor (712) having a gate connected to said memory cell second transistor (716) channel second end and a channel connected between said memory cell first transistor (710) channel second end and a circuit ground potential, and

a fourth transistor (714) having a gate connected to said memory cell first transistor (710) channel second end and a channel connected between said memory cell second transistor (716) channel second end and the circuit ground potential; and

a fifth transistor (720) having a gate connected to said memory cell second transistor (716) channel second end and a channel connected from said memory cell first transistor (710) channel second end to (734) a power supply potential, and

a sixth transistor (722) having a gate connected to said memory cell first transistor (710) channel second end and a channel connected from said memory cell second transistor (716) channel second end to (734) the power supply potential a regenerative sense amplifier (804) including,

a regenerative sense amplifier first line (834),

a regenerative sense amplifier second line (836),

a first transistor (812) having a gate connected to said second bit line (440) and a channel connected between said first bit line (430) and said regenerative sense amplifier second line (836),

a second transistor (814) having a gate connected to said first bit line (430) and a channel connected between said second bit line (440) and said regenerative sense amplifier second line (836),

a third transistor (820) having a gate connected to said second bit line (440) and a channel connected between said regenerative sense amplifier first line (834) and said first bit line (430), and

a fourth transistor (822) having a gate connected to said first bit line (430) and a channel connected between said regenerative sense amplifier first line (834) and said second bit line (440).

7. A static, random access memory circuit as recited in claim 6 wherein said regenerative sense amplifier (804) further includes,

a first sense amplifier selecting line (866),

a second sense amplifier selecting line (876),

a fifth transistor (860) having a gate connected to said regenerative sense amplifier first sense amplifier selecting line (866) and a channel connected between said regenerative sense amplifier first line (834) and the power supply potential (864) and

a sixth transistor (862) having a gate connected to said regenerative sense amplifier second sense amplifier selecting line (876) and a channel connected between said regenerative sense amplifier second line (836) and the circuit ground potential.

8. A static, random access memory circuit as recited in claim 7 wherein said memory cell first (710), second (716), third (712), and fourth (714) transistors each have a channel width which is within fifty percent of a predetermined width.

9. A static, random access memory circuit as recited in claim 6 wherein said memory cell first (710), second (716), third (712), and fourth (714) transistors each have a channel width which is within fifty percent of a predetermined width.

10. A static, random access memory circuit as recited in claim 6 further comprising a bit lines equalization circuit.