Digital signal receiving circuit with means for controlling a baud rate sampling phase by a power of sampled signals

• US 5,048,060 A
• Filed: 11/16/1988
• Issued: 09/10/1991
• Est. Priority Date: 11/16/1987
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Yamaguchi, Masaru, Arai, Masanobu, Ogata, Takenori
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Smith, Ralph
• Application Number:
  US07/271,979
• Time in Patent Office: 1,028 Days
• Field of Search: 375/96, 375/106, 375/110, 375/118, 375/14, 375/111, 364/728.07
• US Class Current: 375/355
• CPC Class Codes: H04L 7/0054 Detection of the synchronisation error by features other than the received signal transition by means of signal transition H04L7/033
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions

Abstract

In a baude rate sampling type receiving circuit for use in a system for transmitting digital data signal at a transmission baude rate, in order to control the sampling phase at the optimum phase, desired elements of an autocorrelation function of a series of baud rate sampled signals are calculated and are linearly summed by a calculating circuit to provide a linear summation as a power of the series of sampled signals. The sampling phase at the baud rate sampling is controlled by a control circuit by use of the linear summation so that the power is maximized, whereby the sampling phase is maintained at the optimum sampling phase.

Claims

1. A receiving circuit for use in a transmission system of a digital signal at a transmission baud rate, said receiving circuit comprising:

a baud rate sampling circuit for sampling said digital signal as a received signal by a sampling signal having a sampling rate equal to said transmission baud rate to produce a series of sampled signals;

calculating means, operatively connected to said baud rate sampling circuit, for calculating at least one element of an autocorrelation function of said series of sampled signals as a power of said series of sampled signals; and

sampling control means responsive to said power for controlling a sampling phase of said sampling signal so that said power is maximized.

2. A receiving circuit as claimed in claim 1, wherein said calculating means calculates a plurality of elements of said autocorrelation function of said series of sampled signals, and calculates a linear sum of said plurality of elements of said autocorrelation function as said power.

3. A receiving circuit as claimed in claim 1, wherein said receiving circuit further comprises digital filter means for filtering said series of sampled signals.

4. In a receiving circuit for use in a transmission system of a digital signal at a transmission baud rate, said receiving circuit comprising a baud rate sampling circuit for sampling said digital signal as a received signal by a sampling signal having a sampling rate equal to said transmission baud rate to produce a series of sampled signals, wherein the improvement comprises:

calculating means coupled with said baud rate sampling circuit for performing an autocorrelation function and for calculating a linear summation of predetermined elements of an autocorrelation function of said series of sampled signals as a power of said series of sampled signals, said calculating means comprising first means for calculating said predetermined elements of the autocorrelation function of said series of sampled signals to produce calculated data signals, second means for summing said calculated data signal to produce a summed data signal, and third means for integrating said summed data signal for a predetermined time period to produce an integrated signal as said linear summation; and

sampling control means responsive to said power for controlling a sampling phase of said sampling signal so that said power is maximized.

5. A receiving circuit as claimed in claim 4, which further comprises a digital filter for filtering and delivering said series of sampled signals to said calculating means.

6. A receiving circuit as claimed in claim 5, wherein said digital filter has a filtering characteristic of (1-D).

7. A receiving circuit as claimed in claim 4, wherein said first means comprises a predetermined number of delay means each having a delaying time equal to a sampling period corresponding to said sampling rate and being connected in a cascade for delaying said series of sampled signals, each delay means delivering delayed signals, and a plurality of multiplying means coupled with said delay means, respectively, to multiply said delayed signals by said series of sampled signals to produce said calculated data signals, respectively.

8. A receiving circuit as claimed in claim 4, wherein said third means comprises adder means for adding said summed data signal and an adding signal to produce an added signal, and delaying means for delaying said added signal to produce said integrated signal, said integrated signal being supplied to said adder means as said adding signal.

9. In a receiving circuit for use in a transmission system of a digital signal at a transmission baud rate, said receiving circuit comprising a baud rate sampling circuit for sampling said digital signal as a received signal by a sampling signal having a sampling rate equal to said transmission baud rate to produce a series of sampled signals, wherein the improvement comprises:

calculating means coupled with said baud rate sampling circuit for performing an autocorrelation function and for calculating a linear summation of predetermined elements of an autocorrelation function of said series of sampled signals as a power of said series of sampled signals, said calculating means comprising a read only memory for memorizing a program for calculating said linear summation, a random access memory for storing said series of the sampled signals, and processing means for executing said calculating program to produce said linear summation as said power in cooperation with said read only memory and said random access memory; and

sampling control means responsive to said power for controlling a sampling phase of said sampling signal so that said power is maximized.