Transmitting commands over a serial link

• US 5,048,062 A
• Filed: 10/30/1989
• Issued: 09/10/1991
• Est. Priority Date: 10/30/1989
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gregg, Thomas A., Skarshinski, Leon
• Primary Examiner(s): Chin, Stephen
• Application Number:
  US07/429,268
• Time in Patent Office: 680 Days
• Field of Search: 375/106, 375/114, 375/116, 370/81, 370/82, 370/83, 370/105.1, 370/105.4, 370/105.5, 370/110.1
• US Class Current: 375/365
• CPC Class Codes: H04L 25/4908 using mBnB codes
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Abstract

An apparatus and method for transmitting commands over a serial link having a switch intermediate a channel and a control unit wherein continuous sequences of idle characters (K.28.5) are sent over the link for maintaining character synchronization. Commands and response information is sent between ports of the switch and the channel and/or the control unit by modifying every other idle character to a modified idle character to which a command or response function has been assigned. In the modification, a selected number of the bits of the idle character are held invariant, and only those bits are varied which form data characters according to the rules of the 8B/10B encoding method. Code points for a total of 124 modified idle characters are disclosed to which a separate command or response may be assigned.

Claims

1. Apparatus for generating commands in a system wherein multi-bit characters are continuously sent from a sender to a receiver to acquire character synchronization, said apparatus comprising:

register means for providing a multi-bit idle character;

bit modifying means connected to said register means for changing selected bits of said multi-bit idle character for forming a command character which is a modification of said multi-bit idle character; and

multiplexing means for forming an ordered set of characters, said ordered set having said multi-bit idle character as a first character and said command character as a second character.

2. The apparatus of claim 1 wherein said register means is a latch in which the bits of each successive multi-bit idle character are inverted from the previously provided multi-bit idle character such that said first character of said ordered set has a first disparity and said second character of said ordered set has a second, opposite disparity.

3. The apparatus of claim 2 wherein said first character of said ordered set is a K28.5⁺ idle character and said second character of said ordered set is a modified K28.5^- idle character.

4. An apparatus for receiving synchronizing multi-bit characters, said apparatus comprising:

a recognition circuit having an input for receiving an ordered set and an output for providing a FUNCTION OUT message, said recognition circuit having detection means for detecting a first idle character in said received ordered set and latch means for providing said FUNCTION OUT message responsive to a second character in said received ordered set;

a first detector in said detection means for detecting an idle character having a first disparity; and

a second detector in said detection means for detecting an idle character having a second, opposite disparity.

5. The apparatus of claim 4 further comprising:

sequence generating means having an input and an output, said sequence generating means generating ordered sets of characters on its output wherein the first character of each ordered set is an idle character and the second character of each ordered set is a modification of said idle character.

6. The apparatus of claim 5 wherein said first detector detects a K28.5⁺ idle character and said second detector detects a K28.5^- idle character.

7. The apparatus of claim 5 wherein said first detector and said second detector have outputs, and said recognition circuit further comprises a synchronization means connected to the outputs of said first and second detectors, said synchronization means for synchronizing said first and second detectors until one of said first or second detectors detects a first idle character of one of said ordered sets.

8. The apparatus of claim 7 wherein said recognition circuit further comprises a state machine connected to the outputs of said first and second detectors, said state machine having an error state representative of two idle characters having the same disparity being detected in a row.

9. The apparatus of claim 8 wherein said latch means latches selected ones of the most significant bits of said second character as said FUNCTION OUT message.

10. The apparatus of claim 9 wherein said detection means further comprises a third detector for detecting a selected sub-block of least significant bits of said second character, said selected sub-block of least significant bits being selected to be invariant in selected available characters of said second character.

11. The apparatus of claim 10 wherein said third detector has an output connected to said state machine, said state machine having an idle detect state representative of an idle character being detected by said detection means, and a FUNCTION OUT state representative of said sub-block being detected by said third detector, said state machine only allowing state moves to said FUNCTION OUT state from said idle detect state such that FUNCTION OUT messages are provided upon the detection of said ordered sets.

12. A method of selecting a second character of an ordered set wherein the first character of said ordered set is an idle character and the second characters is a command character, said method comprising the steps of:

a. establishing said idle character as a base character;

b. arranging all valid 8B/10B data characters in sequence such that the first 8B/10B data character has the maximum number of its least significant bits in the same pattern as the base character and the last 8B/10B data character in the sequence has none of its least significant bits in the same pattern as the base character; and

c. selecting the number of 8B/10B data characters in the sequence as the number of command characters desired such that the maximum number of least significant bits of the command characters are invarient from the base character.

13. A data transmission apparatus synchronized by the continuous transmission of multi-bit characters, said data transmission apparatus comprising:

a switch having at least two ports; and

a switch controller for controlling switching between said ports by said switch;

each of said ports including an input for receiving data characters transmitted to said port and an output for sending data characters transmitted from said port;

each of said ports further including a recognition circuit having an input for receiving an ordered set of said multi-bit characters from its attached link and an output connected to said switch controller for providing to said switch controller a FUNCTION OUT message, said recognition circuit having detection means for detecting a first idle character in said received ordered set, and latch means for providing said FUNCTION OUT message responsive to a second character in said received ordered set.

14. The data transmission system of claim 13 wherein said detection means comprises a first detector for detecting an idle character having a first disparity, and a second detector for detecting an idle character having a second, opposite disparity.

15. The data transmission apparatus of claim 14 wherein said first detector detects a K28.5⁺ idle character and said second detector detects a K28.5^- idle character.

16. The data transmission apparatus of claim 15 wherein said first detector and said second detector have outputs, and said recognition circuit further comprises a synchronization means connected to the outputs of said first and second detectors, said synchronization means for synchronizing said first and second detectors until one of said first or second detectors detects a first idle character of one of said ordered sets.

17. The data transmission apparatus of claim 16 wherein said recognition circuit further comprises a state machine connected to the outputs of said first and second detectors, said state machine having an error state representative of two idle characters having the same disparity being detected in a row.

18. The data transmission apparatus of claim 17 wherein said latch means latches selected ones of the most significant bits of said second character as said FUNCTION OUT message.

19. The data transmission apparatus of claim 18 wherein said detection means further comprises a third detector for detecting a selected sub-block of least significant bits of said second character, said selected sub-block of least significant bits being selected to be invariant in selected available characters of said second character.

20. The data transmission apparatus of claim 19 wherein said third detector has an output connected to said state machine, said state machine having an idle detect state representative of an idle character being detected by said detection means, and a FUNCTION OUT state representative of said sub-block being detected by said third detector, said state machine only allowing state moves to said FUNCTION OUT state from said idle detect state such that FUNCTION OUT messages are provided upon the detection of said ordered sets.

21. The data transmission apparatus of claim 20 further comprising:

sequence generating means having an input and an output, said sequence generating means generating ordered sets of characters on its output wherein the first character of each ordered set is an idle character and the second character of each ordered set is a modification of said idle character.

22. The data transmission apparatus of claim 13 further comprising:

a link attached to each port, each of said links having two data transmission conductors, one data transmission conductor connected to the input of the attached port for transmitting data to the attached port and the other data transmission conductor connected to the output of the attached port for transmitting data from the attached port; and

a link-level facility attached to each link for sending data to and receiving data from the attached port.