Testing of integrated circuits using clock bursts
First Claim
1. A method of testing an electronic circuit having a plurality of sequential logic elements comprising the steps of:
- applying test signals to logic input terminals of the circuit;
observing output signals at output terminals of the circuit so that the output signals are in a known state;
applying at least two clock signals to a clock input terminal of the circuit at a predetermined frequency;
observing the output signals at the output terminals of the circuit during a period when no clock signals are applied for purposes of testing the circuit; and
comparing the output signals to expected output signals to determine if the circuit functions at the predetermined frequency for substantially all the elements of the plurality of sequential logic elements.
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Accused Products
Abstract
A method of testing integrated circuits at high operating speeds is provided which is applicable to sequential logic circuits such as ASICs. A general purpose ASIC tester applies test vectors to the integrated circuit under test. The logic input signals are held unchanged and a series of high speed clock signals (a clock burst) are applied to the clock terminals of the integrated circuit. These clock signals are provided at the speed at which it is desired to test the integrated circuit. Then the output terminals are observed to determined if the device is in the expected state (as determined by simulation) after the clock burst. The process is repeated until no further output terminals change state, and then the device may be reinitialized and another series of state changes initiated. Thus every path in the circuit may be tested at high speed by a conventional low speed tester.
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Citations
9 Claims
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1. A method of testing an electronic circuit having a plurality of sequential logic elements comprising the steps of:
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applying test signals to logic input terminals of the circuit; observing output signals at output terminals of the circuit so that the output signals are in a known state; applying at least two clock signals to a clock input terminal of the circuit at a predetermined frequency; observing the output signals at the output terminals of the circuit during a period when no clock signals are applied for purposes of testing the circuit; and comparing the output signals to expected output signals to determine if the circuit functions at the predetermined frequency for substantially all the elements of the plurality of sequential logic elements. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification