Electronically reconfigurable digital pad attenuator using segmented field effect transistors

• US 5,049,841 A
• Filed: 07/11/1990
• Issued: 09/17/1991
• Est. Priority Date: 07/11/1990
• Status: Expired due to Fees

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: General Electric Company
• Inventors: Jacomb-Hood, Anthony W., Bourdelais, Paul A., Cooper, Paul D., Windyka, John A., Helms, David R., Naster, Ronald J.
• Primary Examiner(s): GENSLER, PAUL L
• Application Number:
  US07/551,067
• Time in Patent Office: 433 Days
• Field of Search: 333/81 R, 333/81 A, 307/567, 307/568
• US Class Current: 333/81.00R
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated
• CPC Class Codes: H03H 11/245 using field-effect transistor
• CPC Class Codes: H03H 7/25 comprising an element controlled by an electric or magnetic variable H03H7/27 takes precedence

Abstract

An electronically reconfigurable digital pad attenuator is disclosed using selectively controlled segmented field effect transistors in a passive, non-gain state as the principal impedance elements. The attenuator may be fabricated in the monolithic microwave integrated circuit (MMIC) format with a segmented gate field effect transistor being connected in each of the separate branches of a Pi pad, Tee pad, or Bridged Tee pad attenuator configuration. The individual FET segments are maintained in a high admittance "ON" state or a low admittance "OFF" state in accordance with the binary control potentials applied to the gate of each segment, the principal electrodes being maintained at a zero potential difference. The attenuation then becomes a function of the binary gate potentials applied to each segment and assumes one of a set of well-defined discrete values. The attenuator consumes minimum power, provides attenuation steps that are independent of GaAs MMIC fabrication process tolerances, i.e. lot to lot stable, is wide band, is well matched at input and output terminals, and facilitates setting nominal gain in microwave and millimeter wave subsystems while minimizing transmission phase variations without degrading dynamic range, extending dynamic range in communications receivers, and wide band accuracy in vector modulators.

Claims

1. An electronically reconfigurable Pi-pad attenuator providing a set of discrete attenuation states (S21 values) comprising

A) a monolithic crystalline substrate suitable for forming mutually insulated metallizations and field effect transistors,

B) a first metallization on said member forming a first note for application of an input signal and for internal signal connection,

C) a second metallization forming a second node for internal signal connection and for derivation of an output signal,

D) a third metallization forming a third node providing a common signal return for input, output and internal signals,

E) three segmented single gate field effect transistors (FETs) formed on said substrate, each subdivided into a first (m), second (n) and third (o) plurality of selectively controlled FET segments respectively, each segment having a predetermined width to achieve a desired admittance and including

(1) a first region having a first electrode in ohmic contact with said substrate,

L(2) a second region, spaced from the first region, having a second electrode in ohmic contact with said substrate, and

(3) a third region positioned between said first and second regions having a third electrode forming a gate for switching said segment to a high admittance "ON" state or to a low admittance "OFF" state in response to the state of a digital control potential,

each of said (m) segments being serially connected between said first and third metallizations in separate parallel paths,

each of said (n) segments being serially connected between said second and third metallizations in separate parallel paths,

each of said (o) segments being serially connected between said first and second metallizations in separate parallel paths,

F) means for maintaining said three metallizations at a common dc potential to facilitate passive, bidirectional conduction by the (m+n+o) segments of said three FETs with certain segments being in a high admittance "ON" state and other segments being in a low admittance "OFF" state in response to a binary control potential applied to the gate of each segment thereof, and

G) a plurality of control terminals for applying said binary control potential to the gate of each of said (m+n+o) segments, selected combinations of binary control potentials producing particular attenuation states for said attenuator.

2. The attenuator set forth in claim 1, wherein

said first and second FETs nave an equal number of segments (i.e. m=n), the respective first segments being equal, the respective second segments being equal, . . . and the respective m^th segments being equal,

and wherein an (m+o) fold plurality of control terminals are provided, the m gate electrodes of the like dimensioned segments of said first and second FETs being connected to "m" control terminals in matched pairs to insure that said first and second FETs share equal admittance states, and the "o" gate electrodes of said third FET being individually connected to said "o" control terminals.

3. The attenuator set forth in claim 1, wherein

a first resistor is provided connected between said first and third metallizations,

a second resistor having a value equal to that of said first resistor is provided connected between said second and third metallizations, and wherein

a third resistor is provided connected between said first and second metallizations,

said three resistors being selected to set the minimum admittances between said respective pairs of metallizations.

4. An attenuator as set forth in claim 3 for providing linear operation over an increased range of input signal power, wherein

(m+n+o) signal voltage dividing resistors are provided, one serially connected with each segment between the respective metallization pairs, the value of each resistance being inversely proportional to the gate width of the associated segment for equal signal division at each segment.

5. An attenuator as set forth in claim 2 having a small signal transfer (S21 ) value compensated for phase wherein

the virtual equivalent of each segment is a first series connected resistor and capacitor when the segment is "OFF", and a second resistor when the segment is "ON", the reactance of said capacitor being high in relation to the resistances of said first and second resistors at the operating frequency, and wherein

a first resistor is provided connected between said first and third metallizations;

a second resistor having a value equal to that of said first resistor is provided connected between said second and third metallizations, and wherein

a third resistor and an inductor are provided connected in series between said first and second metallizations,

the resistances of said three resistors being selected to set the minimum admittances between said respective pairs of metallizations, and the inductance of said inductor is selected to minimize the phase dispersion due to the capacitances of said segments at said operating frequency.

6. The attenuator set forth in claim 3, wherein

said monolithic crystalline substrate is a compound semiconductor having a high electron mobility suited to microwave or millimeter wave operation selected from the III-V and II-VI families.

7. An electronically reconfigurable Tee-pad attenuator providing a set of discrete attenuation states (S21 values), comprising

A) a monolithic crystalline substrate suitable for forming mutually insulated metallizations and field effect transistors,

B) a first metallization on said member forming a first node for application of an input signal,

C) a second metallization forming a second node for internal signal connection,

D) a third metallization forming a third node for derivation of an output signal,

E) a fourth metallization forming a fourth node providing a common signal return for input, output and internal signals,

F) three segmented single gate field effect transistors (FETs) formed on said member, each subdivided into a first (m), second (n) and third (o) plurality of selectively controlled FET segments, respectively, each segment having a predetermined width to achieve a desired admittance and including

(1) a first region having a first electrode in ohmic contact with said substrate,

(2) a second region, spaced from the first region, having a second electrode in ohmic contact with said substrate, and

L(3) a third region positioned between said first and second regions having a third electrode forming a gate for switching said segment to a high admittance "ON" state or to a low admittance "OFF" state in response to the state of a digital control potential,

each of said (m) segments being serially connected between said first and second metallizations in separate parallel paths,

each of said (n) segments being serially connected between said second and third metallizations in separate parallel paths, and

each of said (o) segments being serially connected between said second and fourth metallizations in separate parallel paths,

G) means for maintaining said four metallizations at a common dc potential to facilitate passive, bidirectional conduction by the (m+n+o) segments of said three FETs with certain segments being in a high admittance "ON" state and other segments being in a low admittance "OFF" state in response to a binary control potential applied to the gate of each segment thereof, and

H) a plurality of control terminals for applying said binary control potential to the gate of each of said (m+n+o) segments, selected combinations of binary control potentials producing particular attenuation states of said attenuator.

8. The attenuator set forth in claim 7, wherein

said first and second FETs have an equal number of segments (i.e. m=n), the respective first segments being equal, the respective second segments being equal, . . . and the respective m^th segments being equal,

and wherein an (m+o) fold plurality of control terminals are provided, the m gate electrodes of the like dimensioned segments of said first and second FETs being connected to "m" control terminals in matched paris to insure that said first and second FETs share equal admittance states, and the "o" gate electrodes of said third FET being individually connected to said "o" control terminals.

9. The attenuator set forth in claim 8, wherein

a first resistor is provided connected between said first and second metallizations;

a second resistor having a value equal to that of said first resistor is provided connected between said second and third metallizations, and wherein

a third resistor is provided connected between said second and fourth metallizations,

said three resistors being selected to set the minimum admittances between said respective pairs of metallizations.

10. An attenuator as set forth in claim 9 for providing linear operation over an increased range of input signal power, wherein

(m+n+o) signal voltage dividing resistors are provided, one serially connected with each segment between the respective metallization pairs, the value of each resistance being inversely proportional to the gate width of the associated segment for equal signal division at each segment.

11. An attenuator as set forth in claim 8 having a small signal transfer (S21 ) value compensated for phase wherein

the virtual equivalent of each segment is a first series connected resistor and capacitor when the segment is "OFF", and a second resistor when the segment is "ON", the reactance of said capacitor being high in relation to the resistances of said first and second resistors at the operating frequency, and wherein

a first resistor and a first inductor are serially connected between said first and second metallizations;

a second resistor and a second inductor having values equal to those of said first resistor and said first inductor, respectively, are serially connected between said second and third metallizations, and wherein

a third resistor is provided connected in series between said second and fourth metallizations,

the resistances of said three resistors being selected to set the minimum admittances between said respective pairs of metallizations, and the inductance of said inductors are selected to minimize the phase dispersion due to the capacitances of said segments at said operating frequency.

12. The attenuator set forth in claim 9, wherein

said monolithic crystalline substrate is a compound semiconductor having a high electron mobility suited to microwave or millimeter wave operation selected from the III-V or II-VI families.

14. The attenuator set forth in claim 11, wherein

a third resistor is provided connected between said first and third metallizations, and a

a fourth resistor is provided connected between said second and fourth metallizations, and wherein

said two resistors being selected to set the minimum admittances between said respective pairs of metallizations.

15. An attenuator as set forth in claim 14 for providing linear operation over an increased range of input signal power, wherein

(m+n) signal voltage dividing resistors are provided, one serially connected with each segment between the respective metallization pairs, the value of each resistance being inversely proportional to the gate width of the associated segment for equal signal division at each segment.

17. The attenuator set forth in claim 14, wherein

said monolithic crystalline substrate is a compound semiconductor having a high electron mobility suited to microwave or millimeter wave operation selected from the III-V or II-VI families.

13. An electronically reconfigurable bridged Tee-pad attenuator providing a set of discrete attenuation states (S21 values), comprising

A) a monolithic crystalline substrate suitable for forming mutually insulated metallizations and field effect transistors,

B) a first metallization on said substrate forming a first node for application of an input signal,

C) a second metallization forming a second node for internal signal connection,

D) a third metallization forming a third node for derivation of an output signal,

E) a fourth metallization forming a fourth node providing a common signal return for input, output and internal signals,

F) two segmented single gate field effect transistors (FETs) formed on said substrate, each subdivided into a first (m) and second (n) plurality of selectively controlled FET segments, respectively, each segment having a predetermined width to achieve a desired admittance and including

(1) a first region having a first electrode in ohmic contact with said substrate,

(2) a second region, spaced from the first region, having a second electrode in ohmic contact with said substrate, and

(3) a third region positioned between said first and second regions having a third electrode forming a gate for switching said segment to a high admittance "ON" state or to a low admittance "OFF" state in response to the state of a digital control potential,

each of said (m) segments being serially connected between said first and third metallizations in separate parallel paths,

each of said (n) segments being serially connected between said second and fourth metallizations in separate parallel paths,

G) a first and a second resistor of equal values each having one terminal connected to said second metallization, the pair being serially connected between said first and third metallizations,

h) means for maintaining said two metallizations at a common dc potential to facilitate passive, bidirectional conduction by the (m+n) segments of said two FETs with certain segments being in a high admittance "ON" state and other segments being in a low admittance "OFF" state in response to a binary control potential applied to the gate of each segment thereof, and

I) an (m+n) fold plurality of control terminals for applying said binary control potential to the gate of each of said l(m+n) segments, selected combinations of binary control potentials producing particular attenuation states for said attenuator.

16. An attenuator as set forth in claim 13 having a small signal transfer (S21 ) value compensated for phase wherein

the virtual equivalent of each segment is a first series connected resistor and capacitor when the segment is "OFF", and a second resistor when the segment is "ON", the reactance of said capacitor being high in relation to the resistances of said first and second resistors at the operating frequency, and wherein

a first resistor and a first inductor are serially connected between said first and third metallizations;

and

a second resistor and a second inductor are serially connected between said second and fourth metallizations;

the resistances of said first and second resistors being selected to set the minimum admittances between said respective pairs of metallizations, and the inductance of said inductor is selected to minimize the phase dispersion due to the capacitances of said segments at said operating frequency.