Memory cell structure of semiconductor memory device

• US 5,049,956 A
• Filed: 07/06/1990
• Issued: 09/17/1991
• Est. Priority Date: 07/13/1989
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Furukawa, Mitsumasa, Yoshida, Tohru
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Limanek, Robert P.
• Application Number:
  US07/549,081
• Time in Patent Office: 438 Days
• Field of Search: 357/23.5, 357/55
• US Class Current: 257/317
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

In a memory call of an EPROM, a drain region, a channel region, and a source region are formed in a direction perpendicular to the surface of a semiconductor substrate. A trench is provided, which penetrates the drain region and the channel region and reaches the source region. A floating gate and a control gate are formed in the trench, in a direction perpendicular to the surface of the semiconductor substrate.

Claims

1. A memory cell employed in an erasable programmable read-only memory, comprising:

a semiconductor substrate having a surface;

a source region formed on the substrate;

a channel region formed on the source region;

a drain region formed on the channel region;

a trench penetrating the drain region and the channel region, reaching the source region, and extending in a direction substantially perpendicular to the surface of the substrate the trench including an inner surface;

a floating gate comprising a first gate insulating layer formed on the inner surface of the trench, including an inner surface, and a first conductor formed in partial contact with the inside surface of the first gate insulating layer, and including a portion not in contact with the first gate insulating layer; and

a control gate comprising a second gate insulating layer formed on the portion of the first conductor which is not in contact with the first gate insulating layer, and a second conductor formed on the second gate insulating layer opposite to the portion in contact with the first conductor;

wherein a portion of the floating gate and a portion of the control gate project perpendicularly from the surface of the semiconductor substrate.

2. The memory cell according to claim 1, also including an insulating layer on the drain region having a predetermined thickness such that the capacitance between the floating gate and the control gate is at a predetermined value.

3. The memory cell according to claim 1, wherein said control gate projects from the substantial surface of the substrate.

4. The memory cell according to claim 1, wherein said read-only memory is an electrically erasable programmable read-only memory.