Shielded front end receiver circuit with IF amplifier on an IC

• US 5,050,238 A
• Filed: 07/11/1989
• Issued: 09/17/1991
• Est. Priority Date: 07/12/1988
• Status: Expired due to Term

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Saeki, Takao, Sugayama, Sakae, Tomizuka, Kazuo, Sandoh, Fumio
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): Charonel, Lisa
• Application Number:
  US07/378,397
• Time in Patent Office: 798 Days
• Field of Search: 455/300, 455/301, 455/325, 455/333, 455/313, 357/48, 357/45, 357/84
• US Class Current: 455/300
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H04B 1/16 Circuits

Abstract

A semiconductor integrated circuit for a radio comprises: a front end circuit block (1) including at least an oscillation circuit (1b) and a mixing circuit (1c), for converting an RF signal to an IF signal; and an IF amplifying circuit block (2) for amplifying the IF signal and limiting an amplitude thereof, and the front end circuit block (1) is covered with shield electrodes (17, 17a, 17b, 17c) connected to a predetermined potential.

Claims

1. A semiconductor integrated circuit for a radio receiver, comprising:

a front end circuit block which includes at least an oscillation circuit and a mixing circuit for converting a radio frequency signal to an intermediate frequency signal, said front end circuit block being formed in a region of a semiconductor chip, said oscillation circuit being formed in a corner of said semiconductor chip;

an amplifying circuit block formed in another region of said chip for amplifying said intermediate frequency signal and limiting an amplitude thereof, said blocks being separated from each other for reducing mutual interference from arising as between said blocks;

a plurality of shield electrodes for absorbing undesirable radiation generated from said first end circuit block and for absorbing undesirable radiation which would be otherwise interfer with said front end circuit block, said shield electrodes covering said front end circuit block, one of said shield electrodes covering only said oscillation circuit;

a dedicated contact pad connected to the one shield electrode; and

other contact pads which are connected to the other of said shield electrodes, said dedicated contact pad and said other contact pads being different and separated from each other so as to avoid having a common conductor impedance with each other.

2. A circuit as in claim 1, wherein absorption electrodes for absorbing leakage current from p⁺ isolation regions are provided under said shield electrodes, said absorption electrodes being connected at a ground potential by means of said shield electrodes.

3. A circuit as in claim 1, further comprising:

a plurality of mats formed in the semiconductor chip as regions which contain a plurality of circuit elements, said regions being separated from each other by respective partitioned areas of said semiconductor chip;

an electronic circuit formed in said semiconductor chip and having a plurality of circuit blocks each having different functions, each of said circuit blocks having a respective plurality of said circuit elements which are electrically connected to each other, said front end circuit block being formed in a respective one of said regions and that is substantially the same size as an area occupied by a plurality of said mats; and

means for powering and grounding said electronic circuit, said powering and grounding means including power and ground lines extending on said partitioned areas.

4. A circuit as in claim 3, wherein said semiconductor chip has first and second conductive layers, said mats each having interconnection lines extending between said semiconductor elements which are contained on said mats, respectively, said interconnection, powering and grounding lines all being formed by conductors within the first conductive layer, said second conductive layers having conductors which form said shield electrodes and further interconnection lines which extend between said mats and said front end circuit block.

5. A circuit as in claim 3, wherein said semiconductor chip has first, second and third conductive layers, said mats each having interconnection lines extending between said semiconductor elements which are contained on said mats, respectively, said interconnection, powering and grounding lines all being formed by conductors within the first conductive layer, said second conductive layers having conductors which form further interconnection lines which extend between said mats and between said mats and said front end circuit block, said third conductor layer having conductors which form said shield electrodes.

6. A circuit as in claim 5, wherein said front end circuit block is formed in a respective plurality of said mats.

7. A circuit as in claim 1, wherein said front end circuit block (1) and said amplifying circuit block (2) are disposed with a spacing in a diagonal direction of a rectangular semiconductor chip.

8. A semiconductor integrated circuit in accordance with claim 1, comprising:

mat regions (A-J, N-T) of a substantially equal size formed on a semiconductor chip (11) and each including a plurality of circuit elements,

partitioned regions (44) for spacing said mats (A-J, N-T) from each other, and

a pair of power supply line (14a) and ground line (15a) disposed on each of said partitioned regions (44), wherein

said front end circuit block (1) is formed in a circuit region substantially equal to an area occupied by an integral number of said mats.

9. A semiconductor integrated circuit in accordance with claim 8, wherein

said power supply lines (14a, said ground lines

said power supply lines (14a), said ground lines (15a), and interconnection lines in said mats (A-J, N-T) and in said front end circuit block (1) are formed by conductors in a first conductor layer, and

interconnection lines between said mats (A-J, N-T) and between each said mat (A-J, N-T) and said front end circuit block (1), and said shield electrodes (17, 17a, 17b, 17c) are formed substantially by conductors in a second conductor layer.

10. A semiconductor integrated circuit in accordance with claim 8, wherein

said power supply lines (14a), said ground lines (15a), and interconnection lines in said mats (A-T) are formed by the conductors in the first conductor layer,

interconnections between said mats (A-T) are formed by the conductors in the second conductor layer, and

said shield electrode (17) is formed by a conductor in a third conductor layer.

11. A semiconductor integrated circuit for a radio receiver as in claim 1 wherein said circuit blocks are formed on a semiconductor chip, said semiconductor chip formed with,

at least the front end circuit block (1) of said circuit blocks being surrounded by a dummy island, a reverse bias electrode for applying a predetermined reverse bias potential to said dummy island, and a shield electrode covering said front end circuit block and connected to said reverse bias electrode.