Imaging system

• US 5,051,738 A
• Filed: 02/27/1989
• Issued: 09/24/1991
• Est. Priority Date: 02/27/1989
• Status: Expired due to Fees

• Current Assignee: Revtek, Inc.
• Original Assignee: Revtek, Inc.
• Inventors: Naugler, W. Edward Jr., Tanielian, Aram
• Primary Examiner(s): Brier, Jeffery A.
• Assistant Examiner(s): Wu, Xiao Min
• Application Number:
  US07/315,486
• Time in Patent Office: 939 Days
• Field of Search: 340/718, 340/782, 340/762, 313/499, 313/500, 357/20, 357/17, 357/13
• US Class Current: 345/82
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 33/38 with a particular shape

Abstract

A plurality of semi-conductor diodes disposed in an array may be constructed to emit light when subjected to a particular voltage. This voltage reversely biases the semi-conductor diodes to break down the semi-conductor diodes and to provide for the emission of light upon breakdown. The breakdown occurs at the junction between a pair of electrodes in each semi-conductor diode. One of the electrodes may be an n electrode and the other electrode may be a p electrode. To break down the diode, a positive voltage (e.g. 3-5 volts) may be applied to the n electrode and a ground voltage may be applied to the p electrode. The diodes are so small that an array of 1024×1024 diodes can be disposed in a space approximately 0.4" square to act as pixels. The diodes may be scanned, as in a raster scan, preferably on a repetitive basis. During such scan, individual ones of the diodes receive the breakdown voltage in representation of a visual image to provide a visual display of the image in the pixels defined by the diodes. The emitted light for each pixel is visible at the junction between the p electrode and the n electrode in the diode representing such pixel. The n electrode may be shaped, as in a tear drop, to facilitate the production of the light at such junction, which may be at the pointed end of the tear drop. The light may be formed by the emission of photons when electrons are momentarily trapped in an oxide layer above the junction and then fall back to ground.

Claims

1. In combination for providing a display of a visual image,

a plurality of diodes disposed in contiguous relationships to define an array, each of the diodes constituting a semi-conductor having n and p layers disposed relative to each other to define a junction, each of the semi-conductors being constructed to emit light at the jnction between the n and p layers when a particular voltage is applied between the n and p layers in the semi-conductor to reverse bias the diode, and

means for applying the particular voltage between the n and p layers in individual ones of the diodes in the array to reverse bias the individual diodes in accordance with the visual image to be displayed on the array.

2. In a combination as set forth in claim 1,

the n layer having substantially a tear drop configuration with a pointed end, the pointed end being disposed at the junction of the n layer with the p layer.

3. In a combination as set forth in claim 1,

terminals for the n layer and the p layer being disposed in each diode at positions displaced from the junction between the p layer and the n layer to provide for the illumination of light at such junction.

4. In a combination as set forth in claim 1,

means for providing a raster scan of the diodes in the array, and

means for applying voltages between the n and p layers of individual ones of the diodes in the array during such scan to obtain the production of the white light from such individual diodes at the junctions between the p and n layers in such diodes.

5. In a combination as set forth in claim 1,

the array of diodes being defined by rows and columns,

means for applying a voltage to the n layers in the diodes in a particular column in the array, and

means for applying a voltage to the p layers in the diodes in a particular row in the array to obtain the particular voltage between the n and p layers in the diode common to the particular row and the particular column and to obtain the emission of light from the diode common to the particular row and the particular column at the junction between the p and n layers in such diode.

6. In a combination as set forth in claim 1, the semi-conductor being made from silicon.

7. In combination for providing a display of a visual image,

a plurality of diodes disposed in contiguous relationship to define an array, each of the diodes constituting a semi-conductor having n and p layers disposed relative to each other to define a junction, each of the semi-conductors being constructed to emit light at the junction between the n and p layers when a particular voltage is applied between the n and p layers in the semi-conductor, and

means for applying the particular voltage between the n and p layers in individual ones of the diodes in the array in accordance with the visual image to be displayed on the array,

each of the diodes being constructed to provide an n type body, a p layer on the body, an n layer on the p layer and a p+ layer partially on the body and partially on the n layer and the junction being between the p+ layer and the n layer.

8. In a combination as set forth in claim 7,

the n layer having substantially a tear drop configuration with a pointed end and the pointed end being disposed at the junction of the n layer with the p+ layer.

9. In a combination as recited in claim 7,

terminals for the n layer and p+ layer being disposed in each diode at positions displaced from the junction between the p+ layer and the n layer to provide for the illumination of light at such junction, and

an electrically insulating layer disposed on the body in partially overlapping relationship with the n layer and in partially overlapping relationship with the p+ layer.

10. In a combination as set forth in claim 9,

means for providing a raster scan of the diodes in the array, and

means for applying the particular voltage between the n and p+ layers of individual ones of the diodes in the array during such scan to obtain the production of the white light from such individual diodes at the junction between the p^t and n layers in such diodes.

11. In combination for providing a display of a visual image,

an array of semi-conductors each having an n layer and a p layer and a junction between the n and p layers and each constructed to emit white light at such junction when subjected to a particular voltage between the n layer and the p layer to reverse bias such semi-conductor,

means for providing a scan of the semi-conductors in the array to provide for the activation of successive semi-conductors in the array, and

means for providing for the introduction of the particular voltage between the n and p layers in individual ones of the semi-conductors in the array to obtain the emission of white light from such individual ones of such semi-conductors at the junction between the n and p layers in such individual semi-conductors during such scan in accordance with the visual image to be displayed.

12. In a combination as set forth in claim 11,

each of the semi-conductors in the array being constructed to emit light when subjected to the particular voltage to reverse bias the semi-conductor and each of the semi-conductors being formed from silicon.

13. In a combination as set forth in claim 11,

the array of semi-conductors being formed on a semi-conductor chip made from silicon.

14. In a combination as set forth in claim 11,

an integrated circuit chip,

the semi-conductors in the array being disposed on the integrated circuit chip in an adjacent relationship defining sucessive rows and columns and the scanning means providing for a raster scan of the semi-conductors in the successive rows.

15. In a combination as set forth in claim 14,

each of the semi-conductors providing for the introduction of a positive voltage to the n layer in such semi-conductor and a negative voltage to the p layer in such semi-conductor to obtain the particular voltage and providing for the emission of the white light at the junction of the n layer and the p layer in the semi-conductor when the particular voltage is applied between the n layer and the p layer and the n layer being shaped at the junction with the p layer to provide a field strength for facilitating the production of the white light at such junction.

16. In combination for providing a display of a visual image,

an array of semi-conductor diodes, each diode being constructed to break down when subjected to a particular reverse bias voltage cross the diode and to become illuminated upon breakdown, the diodes in the array being disposed in a particular relationship to define rows and columns,

means for introducing a first voltage to the diodes in an individual column in the array in accordance with the visual image, and

means for introducing a second voltage to the diodes in an individual row in the array to obtain the production of the particular reverse bias voltage across the diode common to the individual column and the individual row for breaking down the diode.

17. In a combination as set forth in claim 16,

the array of semi-conductors being formed on a semi-conductor chip made from silicon.

18. In a combination as set forth in claim 16,

each of the diodes having first and second layers constructed to have voltages applied to them in the particular reverse bias relationship and each of the diodes being constructed to break down when the layers are subjected to voltages having a voltage difference at least equal to the particular reverse bias voltage and the first and second layers in each diode being constructed to define a junction and the junction in each diode being illuminated when the diode breaks down.

19. In a combination as set forth in claim 18,

the first and second layers in each diode respectively constituting n and p layers and a terminal being coupled to the n layer in each diode and a terminal being coupled to the p layer in each diode and the illumination in each diode being provided at the junction between the n layer and the p layer and the first voltage being applied to the terminals coupled to the n layer in the diodes in an individual one of the columns and the second voltage being applied to the terminal coupled to the p layer in the diodes in an individual one of the rows.

20. In a combination as set forth in claim 19,

the n layer in each diode being provided with a configuration to facilitate the production of the white light at the junction between the n and p layers in the diode.

21. In a combination as set forth in claim 19,

the junction between the first and second layers in each diode being displaced from the terminals for such diode to provide for an illumination of such junction when the diode breaks down.

22. In a combination as set forth in claim 21,

each diode being formed form a body constituting an n type, the p layer being disposed on the body and the n layer being disposed on the p layer and a p+ layer being disposed partially on the n layer and partially on the p layer and the junction being provided between the n layer and the p+ layer.

23. In a combination as set forth in claim 22,

an electrically insulating layer disposed in each diode partially on the n layer and partially on the p+ layer in such diode, and

the n layer in each diode being provided with a configuration to facilitate the production of the white light at the junction between the p and n layers in such diode.

24. In combination for emitting light,

an integrated circuit chip made from a semi-conductive material constituting an n type,

a p layer formed on the integrated circuit chip,

an n layer formed on the integrated circuit chip in a particular relationship to the p layer to define a junction with the p layer,

a p+ layer disposed partially on the p layer and partially on the n layer to define a junction with the n layer for the emission of visible light from the junction between the p layer and the n layer upon the production of a particular voltage between the p layer and the n layer,

first terminal means formed on the integrated circuit chip substantially at the position of the p layer to contact the p+ layer and the p layer and made from an electrically conductive material, and

second terminal means formed on the integrated circuit chip at the position of the n layer and made from an electrically conductive material, and

means for introducing voltages to the first and second terminal means to obtain the emission of the visible light at the junction between the p and n layers.

25. In a combination as set forth in claim 24,

the semi-conductor material in the integrated circuit chip constituting silicon.

26. In a combination as set forth in claim 24,

the voltage introducing means reverse biasing the p layer and the n layer with the particular voltage to obtain the emission of the visible light at the junction between the p and n layers in accordance with such reverse biasing.

27. In a combination as set forth in claim 26,

means for applying a positive voltage of a particular magnitude to the second terminal means relative to the voltage applied to the first terminal means to reverse bias the n and p layers with the particular voltage and to obtain the emission of visible light in accordance with such reverse biasing.

28. In a combination as set forth in claim 24,

means for applying a positive voltage of a particular magnitude to the second terminal means relative to the voltage applied to the first terminal means to obtain the emission of visible light from the junction between the n layer and the p layer.

29. In a combination as set forth in claim 28,

a layer of an electrically insulating material disposed partially on the n layer and partially on the p+ layer and covering the junction between the n layer and the p+ layer.

30. In a combination as recited in claim 29,

the integrated circuit chip being made from silicon and

the insulating material being made from silicon dioxide.

31. In a combination as set forth in claim 30,

each of the terminal means being formed from a first layer of an electrically conductive material and a second layer of an electrically conductive, chemically inert material with properties of adhering to the first layer of the electrically conductive material.

32. In a combination as set forth in claim 31,

the first layer of each terminal means being titanium or tungsten, and

the second layer of each terminal means being gold.