Driving circuit for an image display apparatus with improved yield and performance

• US 5,051,739 A
• Filed: 09/22/1989
• Issued: 09/24/1991
• Est. Priority Date: 05/13/1986
• Status: Expired due to Term

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Yamasaki, Mitsuhiro, Hayashida, Toshiaki, Takesada, Hajime
• Primary Examiner(s): Brier, Jeffery A.
• Application Number:
  US07/411,234
• Time in Patent Office: 732 Days
• Field of Search: 340/718, 340/719, 340/765, 340/784, 340/783, 340/785-788, 340/811, 350/331 R, 350/332, 350/333, 358/230, 358/236, 358/241
• US Class Current: 345/90
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2330/08 Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
• CPC Class Codes: G09G 3/30 using electroluminescent panels
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

A driving circuit for an image display apparatus wherein the respective rows and columns of the active matrix panel with a plurality of picture elements disposed on the matrix shape are respectively selected by the clock pulses of the given frequency to drive each of the picture elements. A counter which counts the clock pulses to introduce the binary count values and the inversion outputs, and a decoder which decodes the counter outputs to generate the pulses that sequentially shift in synchronous relation in the clock pulses are provided to feed the counter output from both the ends of the code signal line of the decoder so that the decoder may be always operated normally.

Claims

1. A driving circuit for an image display apparatus of a panel with a plurality of picture elements disposed in a matrix shape, said driving circuit comprising:

a circuit generating pulses which sequentially shift in a synchronous relation with clock pulses to sequentially select, at a period of the clock pulse of a given frequency, respectively each row and/or each column of the panel; and

an output circuit amplifying the pulses to output to said panel, said output circuit including a first FET in which said pulses are input to a gate, and a second FET connected in series with the first FET and in which signals opposite in phase to said pulses are to be input to a gate, so that an output signal is output from a connection point of both FETs.

2. A driving circuit for an image display apparatus of an active matrix panel, with a plurality of picture elements being disposed in matrix shape, respective rows and columns of said active matrix panel are respectively selected by a clock pulse of a given frequency to drive each of said picture elements, the driving circuit comprising:

a counter counting said clock pulses and outputting binary count values and inverted binary count values for said respective rows and columns;

a decoder decoding the binary and inverted binary count value from the counter to simultaneously generate a pair of pulses opposite in polarity, said pair of pulses sequentially shifting in a synchronous relation to said clock pulses in each of said respective rows and/or respective columns; and

an output circuit including first and second FETs being connected in series, a pair of pulses opposite in polarity being applied respectively upon each gate of each FET, output signals amplified from connection points of both FETs being output to said active matrix panel.

3. A driving circuit for an image display apparatus of an active matrix panel, with a plurality of picture elements being disposed in matrix shape, respective rows and/or columns of said active matrix panel are respectively selected by clock pulses of a given frequency to drive the respective picture elements, the driving circuit comprising:

a counter counting said clock pulses and outputting binary count values and inverted binary count values; and

a pair of decoders are respectively connected at both ends of each of the rows and/or both ends of each of the columns, the decoders decoding the binary and inverted binary count values of the counter to generate pulses, in each of said rows and/or in each of said columns, which sequentially shift in a synchronous relation with said clock pulses, said decoders are formed of a-si thin film transistors.

4. A driving circuit for an image display apparatus of an active matrix panel, with a plurality of picture elements being disposed in matrix shape, respective rows and/or columns of said active matrix panel are respectively selected by clock pulses of a given frequency to drive the respective picture elements, the driving circuit comprising:

a counter counting said clock pulses and outputting binary count values and inverted binary count values; and

a decoder decoding the binary and inverted binary count values of the counter to generate pulses, to each of said rows and/or each of said columns, which sequentially shift in a synchronous relation with said clock pulses to feed said binary and inverted binary count values of said counter from both ends of a code signal line of said decoder, said decoder formed of a-Si thin film transistors.

5. An image display apparatus of an active matrix panel, with a plurality of picture elements being disposed in a matrix shape, respective rows and/or columns of said active matrix panel are respectively selected by clock pulses of a given frequency to drive each of said picture elements, the image display apparatus comprising:

a counter which counts said clock pulses and which outputs binary count values; and

a decoder which decodes the binary count values of the counter to generate pulses, in each of said rows and/or each of said columns, which sequentially shift in a synchronous relation with said clock pulses, both the counter and the decoder being disposed on said active matrix panel, said decoder being composed of an a-Si p channel thin film transistor and an a-Si n channel thin film transistor, which responds to the binary count value of the counter.

6. The image display apparatus in accordance with claim 5, wherein the output circuit of the decoder is composed of the the a-Si p channel thin film transistor and the the n channel thin film transistor.