Multi-layer semiconductor device

• US 5,051,865 A
• Filed: 03/11/1991
• Issued: 09/24/1991
• Est. Priority Date: 06/17/1985
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kato, Takashi
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US07/667,257
• Time in Patent Office: 197 Days
• Field of Search: 361/383, 361/384, 361/386, 361/388, 361/394, 361/414, 361/396, 357/75, 357/76, 357/74, 357/81, 357/82, 174/16.3, 174/52.4
• US Class Current: 361/718
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device

Abstract

A multi-layer semiconductor device which includes a stacked wafer body having a plurality of sets of two semiconductor wafers and a heat sink plate interposed therebetween. An end of the heat sink plate of each set of wafers is exposed at at least one of the side surfaces of the stacked wafer body.

An intermediate connecting circuit is provided for connecting circuits in each of the sets of two semiconductors wafers, the intermediate connecting circuit is provided on at least one side surface other than the surface at which the ends of the heat sink plate are exposed.

Claims

1. A multi-layer semiconductor device comprising:

a stacked wafer body having polished vertically sliced side surfaces, including;

a plurality of sets of two semiconductor wafers having an integrated element formed on each of said semiconductor wafers;

an insulating layer formed on said semiconductor wafer;

transistors directly formed on exposed semiconductor wafers in one of the polished vertically sliced side surfaces of said stacked wafer body for controlling the response of said integrated element on each of said semiconductor wafers; and

a plurality of heat sink plates formed between and contacting said sets of two semiconductor wafers, one back side of each of said semiconductor wafers being formed on and having its entire surface in contact with said heat sink plates, an element-formed side of each of said semiconductor wafers having said insulating layer formed thereon, an end of said heat sink plate of each of said sets of two semiconductor wafers being exposed and projecting from at least one of said surfaces of said stacked wafer body; and

an intermediate connecting circuit, connected to said stacked wafer body, for connecting circuits in each of said sets or two semiconductor wafers, said intermediate connecting circuit being provided on at least one side surface other than the surface at which the ends of said heat sink plates are exposed.

2. A multi-layer semiconductor device according to claim 1, wherein said heat sink plate comprises one of aluminum and copper.

3. A multi-layer semiconductor device according to claim 2, wherein the thickness of said aluminum heat sink plate is approximately 70 μ

m or more, and wherein the thickness of said copper heat sink plate is approximately 42 μ

m or more.

4. A multi-layer semiconductor device according to claim 1, further including a heat sink, wherein said heat sink plates have exposed ends, and wherein said exposed ends of said heat sink plates are connected to said heat sink.

5. A multi-layer semiconductor device according to claim 4, wherein said heat sink plates have extended ends, wherein said heat sink has grooves formed therein, and wherein said connection of said exposed ends of said heat sink plates to said heat sink is carried out by connecting said extended ends of said heat sink plates to said grooves of said heat sink.

6. A multi-layer semiconductor device according to claim 4, wherein the exposed ends of said heat sink plates are fixed at right angles to said heat sink plates, wherein said intermediate connecting circuit being further provided on an opposite side surface from said side surface from which the ends of said heat sink plates project and further includes bonding pads, and wherein said semiconductor device is assembled in a three-dimensional IC package.

7. A multi-layer semiconductor device according to claim 1, wherein one of the side surfaces from which the end of said heat sink plate projects is the back side of the other side surface on which said intermediate connecting circuit is formed.

8. A multi-layer semiconductor device according to claim 7, wherein said intermediate connecting circuit has electrodes embedded in said semiconductor wafers.